Electronics I. The University of Toledo. EECS Department EECS /005 CRN: 15699

Transcription

1 s15s_elct7.fm - 1 Electronics I The University of Toledo EECS Department EECS /005 CRN: Instructor: Anthony D. Johnson Class Location: PL anthony.johnson@utoledo.edu Class Day/Time: MWF/ 9:00 to 9:50 A.M. Office Hours: MWF 2:00-3:00 P.M. Lab Location: NE-1018 Office Location: NH-2049 Lab Day/Time: Please see the schedule on page 4. Office Phone: Credit Hours: 4 Term: Spring 2015 COURSE/CATALOG DESCRIPTION Large-signal and incremental characteristics of the pn diode, BJT, MOSFET and JFET. Large- signal analysis and computer simulation of devices and digital circuits. Logic gate implementation. Laboratory experiments and projects. STUDENT LEARNING OUTCOMES Student Learning Outcomes, as accepted by a vote of all program faculty, are listed on page 6. TEACHING STRATEGIES Face-to-face delivery of lectures and printed handouts are delivered in class. Homework set problems from the textbook, and Lab experiment assignments from the printed Lab Manual and postings on the course website (please see pages 5 and 4 of this syllabus) require written and computer generated reports. PREREQUISITES AND COREQUISITES One prerequisite course: EECS:2300 FOR LEVEL UG WITH MIN. GRADE OF D-. REQUIRED TEXTS AND ANCILLARY MATERIALS Bibliographic citation for the required course textbook is shown on page 3, and for the Lab manual on page 4. TECHNOLOGY REQUIREMENTS Hand held calculators/computers are allowed on examinations, but are not required. UNIVERSITY POLICIES (REQUIRED AS IS) Policy Statement on Non-Discrimination on the basis of Disability (ADA) The University is a equal opportunity educational institution. Please read The University s Policy Statement on Nondiscrimination on the Basis of Disability Americans with Disability Act Compliance.) ACADEMIC ACCOMODATIONS (REQUIRED AS IS) The University of Toledo is committed to providing equal access to education for all students. If you have a documented disability or you believe you have a disability and would like information regarding academic accommodations/adjustments in this course please contact the Student Disabiliti Services Office. ACADEMIC POLICIES Only advice not to miss the classes is offered. Professionals are expected to grow up at some time.

2 s15s_elct7.fm - 2 COURSE EXPECTATIONS In absence of a university wide policy on tardeness, students are let to enter the class room at any time - better late than never. No visits to restrooms are allowed during examination time. Policies on credit for Lab and homework reports are stated on pages 4 and 5 respectively; full credit on late reports is assigned only under exceptional circumstances. No extra credit. Attendance is taken only to encourage students to attend - it works. GRADING No weights are involved. Credit points are equal to percentages, since full credit for the course is 100 points. Distribution of points over Homeworks/Lab/Midterms/Final is given on page 3. Credits for Homework and Lab reports are provided one week after a report s due date. Credits for midterms are provided during the next class following the midterm. Midterm Grading Distribution of the midterms total numbers of points between three problems depends on the content of problems which is variable from semester to semester. Students performance on midterms shows whether they are studying during the whole semester. Final Grading Distribution of the final s total number of points between three problems depends on the content of problems which changes from semester to semester. COMMUNICATION GUIDELINES adresses and phone numbers of the instructor, and Lab assistants and graders are displayed on pages 3 and 4. STUDENT SUPPORT SERVICES Students with inadequate preparation in Mathematics and Physics can benefit from tutoring provided by the institution s academic and student support services. EECS department provides instructors and GAs office hours. COURSE SCHEDULE The course calendar by textbook topics per semester weeks is shown on page 3. Alignment of textbook topics with SLOs is not a straight forward matter for a number of reasons. Description of SLO assessment methods occupies a few pages in the ABET assessment report.

3 Electronics I s15s_elct7.fm - 3 SYLLABUS Week Starting Subject 1. January 12 Chapter 1 Introduction to Electronics Chapter 2 Solid State Electronics Materials 2. January 19 Chapter 3 Solid State Diodes 3. January 26 Chapter 3 Solid State Diode Circuits 4. February 2.Section 3.13 through 3.16 Rectifier circuits. 5. February 9 Chapter 4 Field Effect Transistors Midterm#1 6. February 16 Chapter 6 Introduction to Digital Electronics. 7. February 23 Chapter 7 Static CMOS: 7.1 and 7.2 CMOS Inverter circuit. 8. March 2 Chapter 7 : 7.2 CMOS Inverter circuit. Section 12.3 DAC and 12.4 ADC 9. March 16 Chapter 7 CMOS: 7.5 CMOS NAND and NOR Gates. 10. March 23 Chapter 7 CMOS: 7.6 through 7.10 Design of Complex gates March 30 Chapter 5 Bipolar Junction Transistor. Midterm#2 12. April 6 Chapter 5 Bipolar Junction Transistor. 13. April 13 BJT Inverter 14. April 20 Chapter 9 Bipolar Logic Circuits. 15. April 27 Chapter 8 MOS Memory and storage circuits. Objectivs Prerequisites Understanding the operation of electronic circuit components and their piecewise linear models. Introduction to basic digital circuits, and digital circuit families. Hands-on experience in simulation, test, and measurement of electronic circuits. For more detailed description please see Section 4. EECS 2300 Electric Circuits (with a grade of C or higher, if you want your instructor s advice). Textbook: Jaeger/Blalock: Microelectronic Circuit Design-4th Ed., McGraw-Hill, 2010, ISBN / Exam policy: Two Midterm Exams (of which the first missed midterm is optional), and a mandatory comprehensive Final examination in the final s week. Points for one missed midterm are transferred to the Final s point pool. Missed Final can be taken at the Final s place and time of any semester in which the course is offered. Missing all three examinations results in failing the course. Grading Policy: Homeworks / Lab / two Midterms / Final = 12/24/30/34. Instructor: Dr. A.D. Johnson; office NI-2049; phone x8176. Course webpage: Homework grader Ms, Jahnavi Yalamanchili, office: NE-2042, office hours: MW 11:00 to12.00pm, manchilis@gmail.com. Unless stated otherwise, location of graders office hours: NI-2000 South bridge between towers.

4 2. Lab information 2.1 Lab Room: NE Electronics Lab 2.2 Schedule of Lab Sessions 2.3 Schedule of Lab Assignments 2.4 Lab Assignments s15s_elct7.fm - 4 Section Time GA GA office GA s office hours 3400:002 M 3:00-5:200PM Sahu, Abhishek abhishek.sahu@rockets.utoledo.edu 3400:003 T 2:00-4:20PM Hazari, Noor Ahmad NoorAhmad.Hazari@rockets.utoledo.edu NE :004 W 3:00-5:20PM Sahu, Abhishek NE :005 F 11:00-01:20PM Hazari, Noor Ahmad Description of Experiments: #1 through #14 is provided in the Electronics Lab Manual I, by Dr. R.King, which is available from the campus bookstore. Descriptions of Lab Assignments #9 through #12 are posted on the course webpage. Prelab Assignment. To improve the ratio of the time spent building the experimental circuit on the protoboard to the time devoted to the educational experience through experiments on the built circuit, students are required to prepare (carries 25% of the grade) a good quality, computer generated drawing of the physical layout of circuits to be built. Lab report: Computer generated Lab reports are required for full credit. For details, please see the course webpage. Grading Policy: Prelab Assignment / Lab Experiment / Lab Report = 0.5 / 0.75 / MW 3.00 to 4.00PM NO Office MT to 12.00PM Experiment numbering in this schedule refers to the the Electronics Lab Manual I, by Dr. R.J.King. Semester Lab week Assignment Experiment 3 1 #1 Using the Digital Storage Oscilloscope 4 2 #3 Diodes 5 3 #11 DC Analysis of a Diode Circuit Using SPICE 6 4 #13 Simulation of a bridge rectifier using SPICE 7 5 #14 Diode Reverse Recovery as Observed using SPICE 8 6 #6 SPICE modelling of MOSFET and JFET 9 7 #7 Characterizing Digital Logic gates: VTC, NM and t PD 10 8 #9 Analog/Digital Conversion 11 9 Simulation of a CMOS two-input NAND gate using SPICE Design of an Experiment Pass Transistor Logic Gates Simulation of a TTL two-input NAND gate using SPICE

5 3. Homework schedule 3.1 Minimal Required Homework Problem set s15s_elct7.fm - 5 Numbers in the Problem Set Contents column of the following table refer to the problem designations in the course textbook; descriptions of other assignments/problems are posted on the course webpage. Set # #12 Analysis of the characteristic points on the BJT inverter VTC. 14 * in 4.2 calculate the capacitance per unit area, since the parameters L and W are not specified. The minimum required homework set is the result of a compromise made with the past generations of students who had complained that the double number of problems presented them with too much work. Current students willing to acquire a solid knowledge of the subject are strongly advised to solve twice as many problems, including those from past exams posted on the course homepage. 3.2 Policy on credit for homework assignments For full credit on problem solutions: 3.21 give answers to all questions, Problem Set Contents S emester week due #1 Analysis of problem areas in the exams of previous two semesters. 1 #2 2.2, 2.3, 2.7, 2.9, 2.12, 2.23, #3 2.45, 2.52, 3.1, 3.2, 3.8, 3.13, 3.18; bonus point, 3 #4 3.22, 3.26, 3.35, 3.43, 3.48, 3.51, 3.56, 4 #5 3.58, 3.66, 3.69, 3.71, 3.72, 3.73, #6 3.78, 3.83, 3.86, 3.92, 3.100(a), #7 4.2*, 4.4, 4.6, 4.8, 4.10, 4.15, #8 Analysis of the characteristic points on the CMOS inverter VTC. 9 #9 6.1, 6.2, 6.3, 6.7, 6.8, 6.9, #10 Calculation of I/O Parasitic Capacitances of the CMOS inverter circuit. 12 #11 5.1, 5.2, 5.4, 5.13, 5.31, 5.32, show the original and auxiliary circuit models with circuiit elements labelled by their parameters (which are not the parameter values), 3.23 indicate in the circuit model the positive reference directions of all voltages and currents which are involved in the solution process, 3.24 provide all symbolic and numerical expressions whose evaluation produces shown numerical results, 3.25 apply the determinant method for solving sets of simultaneous algebraic equations.

6 3.3Policy on submission of Homework Reports s15s_elct7.fm This policy promotes good planning habits. The fact that something went wrong the morning of the due day does not make a case for delaying the due time. We ought to be prepared for the day when something unusual happens All homework reports (solutions) are due at the beginning of the last class of the week In order to discourage the practice of preparing the reports during the time scheduled for classes, the absolute deadline for handing in the homework reports is five minutes after the time scheduled for the beginning of the class Homework reports handed in after the deadline, but before the beginning of the first class of the next week are accepted for half credit Homework reports are not considered turned in if they are not completly covered by a completely filled out cover sheet posted at the course webpage. 4. ABET Documentation 4.1 EAC and CAC Student Learning Objectives 1. Students will be able to apply the large signal method of analysis to electronic circuits that contain nonlinear circuit elements: diodes, FETs and BJTs. 2. Students will be able to apply the SPICE simulation method of analysis to electronic circuits that contain nonlinear circuit elements: diodes, FETs and BJTs. 3. Students will be able to design FET and BJT inverter circuits with a required noise margin and fanout, inverters of minimum size, with equal rise and fall times, and with specified logic threshold voltage value. 4. Students will be able to explain the tradeoffs for lowering power dissipation in digital electronic circuits. 5. Students will be able to analyse combinational logic circuits to determine the Boolean function implemented by the circuit, 6. Students will be able to design combinational static CMOS gates so that they implement a desired Boolean function, and to design the transistor aspect ratios so that the CMOS gate has the same rise and fall times as the reference inverter. 7. Students will be able to give examples of the three established principles of encoding the logic/ numeric values in memory cells: by the state of a bistable circuit, by an electrical charge on a capacitance, and by a FET s threshold voltage value. 8. Students will be able to state the challenges and the complexity tradeoffs in the design of modern memory arrays. 9. Students will be able to state the design principles used in legacy TTL and ECL integrated circuits.

7 s15s_elct7.fm Students will be able to conduct experiments in order to collect, analyze, and interpret data. 11. Students will be able to explain the properties of semiconductor materials and the mechanisms of charge transportation in semiconductor materials. 12. Students will be able to design an experiment to measure the propagation delay of a representative of two families of widely used digital logic gates (4xxx series CMOS and 74LSxx series TTL). 13. The student will be able to function effectively on a team with effectiveness being determined as documented in lab reports, instructor observations, and peer ratings. 4.2 ABET Outcomes Supported EAC CAC Outcome Supporting SLOs Outcome Supporting SLOs a 11 b 10, 12 c 3, 6 d 13 e 5 i 9 j 4, 7, 8 k 1, 2 No CAC outcomes are supported 4.3 ABET Description of EAC Outcomes a - b - c - d - e - i - j - k - An ability to apply knowledge of mathematics, science, and engineering. An ability to design and conduct experiments, as well as to analyze and interpret data. An ability to design a system, component, or process to meet desired needs within realistic constraints such as economic, environmental, social, political, ethical, health and safety, manufacturability, and sustainability. An ability to function on multidisciplinary teams. An ability to identify, formulate, and solve engineering problems. A recognition of the need for, and an ability to engage in life-long learning. A knowledge of contemporary issues. An ability to use the techniques, skills, and modern engineering tools necessary for engineering practice.

8 s15s_elct7.fm - 1 Electronics I The University of Toledo EECS Department EECS /005 CRN: Instructor: Anthony D. Johnson Class Location: PL anthony.johnson@utoledo.edu Class Day/Time: MWF/ 9:00 to 9:50 A.M. Office Hours: MWF 2:00-3:00 P.M. Lab Location: NE-1018 Office Location: NH-2049 Lab Day/Time: Please see the schedule on page 4. Office Phone: Credit Hours: 4 Term: Spring 2015 COURSE/CATALOG DESCRIPTION Large-signal and incremental characteristics of the pn diode, BJT, MOSFET and JFET. Large- signal analysis and computer simulation of devices and digital circuits. Logic gate implementation. Laboratory experiments and projects. STUDENT LEARNING OUTCOMES Student Learning Outcomes, as accepted by a vote of all program faculty, are listed on page 6. TEACHING STRATEGIES Face-to-face delivery of lectures and printed handouts are delivered in class. Homework set problems from the textbook, and Lab experiment assignments from the printed Lab Manual and postings on the course website (please see pages 5 and 4 of this syllabus) require written and computer generated reports. PREREQUISITES AND COREQUISITES One prerequisite course: EECS:2300 FOR LEVEL UG WITH MIN. GRADE OF D-. REQUIRED TEXTS AND ANCILLARY MATERIALS Bibliographic citation for the required course textbook is shown on page 3, and for the Lab manual on page 4. TECHNOLOGY REQUIREMENTS Hand held calculators/computers are allowed on examinations, but are not required. UNIVERSITY POLICIES (REQUIRED AS IS) Policy Statement on Non-Discrimination on the basis of Disability (ADA) The University is a equal opportunity educational institution. Please read The University s Policy Statement on Nondiscrimination on the Basis of Disability Americans with Disability Act Compliance.) ACADEMIC ACCOMODATIONS (REQUIRED AS IS) The University of Toledo is committed to providing equal access to education for all students. If you have a documented disability or you believe you have a disability and would like information regarding academic accommodations/adjustments in this course please contact the Student Disabiliti Services Office. ACADEMIC POLICIES Only advice not to miss the classes is offered. Professionals are expected to grow up at some time.

9 s15s_elct7.fm - 2 COURSE EXPECTATIONS In absence of a university wide policy on tardeness, students are let to enter the class room at any time - better late than never. No visits to restrooms are allowed during examination time. Policies on credit for Lab and homework reports are stated on pages 4 and 5 respectively; full credit on late reports is assigned only under exceptional circumstances. No extra credit. Attendance is taken only to encourage students to attend - it works. GRADING No weights are involved. Credit points are equal to percentages, since full credit for the course is 100 points. Distribution of points over Homeworks/Lab/Midterms/Final is given on page 3. Credits for Homework and Lab reports are provided one week after a report s due date. Credits for midterms are provided during the next class following the midterm. Midterm Grading Distribution of the midterms total numbers of points between three problems depends on the content of problems which is variable from semester to semester. Students performance on midterms shows whether they are studying during the whole semester. Final Grading Distribution of the final s total number of points between three problems depends on the content of problems which changes from semester to semester. COMMUNICATION GUIDELINES adresses and phone numbers of the instructor, and Lab assistants and graders are displayed on pages 3 and 4. STUDENT SUPPORT SERVICES Students with inadequate preparation in Mathematics and Physics can benefit from tutoring provided by the institution s academic and student support services. EECS department provides instructors and GAs office hours. COURSE SCHEDULE The course calendar by textbook topics per semester weeks is shown on page 3. Alignment of textbook topics with SLOs is not a straight forward matter for a number of reasons. Description of SLO assessment methods occupies a few pages in the ABET assessment report.

10 Electronics I s15s_elct7.fm - 3 SYLLABUS Week Starting Subject 1. January 12 Chapter 1 Introduction to Electronics Chapter 2 Solid State Electronics Materials 2. January 19 Chapter 3 Solid State Diodes 3. January 26 Chapter 3 Solid State Diode Circuits 4. February 2.Section 3.13 through 3.16 Rectifier circuits. 5. February 9 Chapter 4 Field Effect Transistors Midterm#1 6. February 16 Chapter 6 Introduction to Digital Electronics. 7. February 23 Chapter 7 Static CMOS: 7.1 and 7.2 CMOS Inverter circuit. 8. March 2 Chapter 7 : 7.2 CMOS Inverter circuit. Section 12.3 DAC and 12.4 ADC 9. March 16 Chapter 7 CMOS: 7.5 CMOS NAND and NOR Gates. 10. March 23 Chapter 7 CMOS: 7.6 through 7.10 Design of Complex gates March 30 Chapter 5 Bipolar Junction Transistor. Midterm#2 12. April 6 Chapter 5 Bipolar Junction Transistor. 13. April 13 BJT Inverter 14. April 20 Chapter 9 Bipolar Logic Circuits. 15. April 27 Chapter 8 MOS Memory and storage circuits. Objectivs Prerequisites Understanding the operation of electronic circuit components and their piecewise linear models. Introduction to basic digital circuits, and digital circuit families. Hands-on experience in simulation, test, and measurement of electronic circuits. For more detailed description please see Section 4. EECS 2300 Electric Circuits (with a grade of C or higher, if you want your instructor s advice). Textbook: Jaeger/Blalock: Microelectronic Circuit Design-4th Ed., McGraw-Hill, 2010, ISBN / Exam policy: Two Midterm Exams (of which the first missed midterm is optional), and a mandatory comprehensive Final examination in the final s week. Points for one missed midterm are transferred to the Final s point pool. Missed Final can be taken at the Final s place and time of any semester in which the course is offered. Missing all three examinations results in failing the course. Grading Policy: Homeworks / Lab / two Midterms / Final = 12/24/30/34. Instructor: Dr. A.D. Johnson; office NI-2049; phone x8176. Course webpage: Homework grader Ms, Jahnavi Yalamanchili, office: NE-2042, office hours: MW 11:00 to12.00pm, manchilis@gmail.com. Unless stated otherwise, location of graders office hours: NI-2000 South bridge between towers.

11 2. Lab information 2.1 Lab Room: NE Electronics Lab 2.2 Schedule of Lab Sessions 2.3 Schedule of Lab Assignments 2.4 Lab Assignments s15s_elct7.fm - 4 Section Time GA GA office GA s office hours 3400:002 M 3:00-5:200PM Sahu, Abhishek abhishek.sahu@rockets.utoledo.edu 3400:003 T 2:00-4:20PM Hazari, Noor Ahmad NoorAhmad.Hazari@rockets.utoledo.edu NE :004 W 3:00-5:20PM Sahu, Abhishek NE :005 F 11:00-01:20PM Hazari, Noor Ahmad Description of Experiments: #1 through #14 is provided in the Electronics Lab Manual I, by Dr. R.King, which is available from the campus bookstore. Descriptions of Lab Assignments #9 through #12 are posted on the course webpage. Prelab Assignment. To improve the ratio of the time spent building the experimental circuit on the protoboard to the time devoted to the educational experience through experiments on the built circuit, students are required to prepare (carries 25% of the grade) a good quality, computer generated drawing of the physical layout of circuits to be built. Lab report: Computer generated Lab reports are required for full credit. For details, please see the course webpage. Grading Policy: Prelab Assignment / Lab Experiment / Lab Report = 0.5 / 0.75 / MW 3.00 to 4.00PM NO Office MT to 12.00PM Experiment numbering in this schedule refers to the the Electronics Lab Manual I, by Dr. R.J.King. Semester Lab week Assignment Experiment 3 1 #1 Using the Digital Storage Oscilloscope 4 2 #3 Diodes 5 3 #11 DC Analysis of a Diode Circuit Using SPICE 6 4 #13 Simulation of a bridge rectifier using SPICE 7 5 #14 Diode Reverse Recovery as Observed using SPICE 8 6 #6 SPICE modelling of MOSFET and JFET 9 7 #7 Characterizing Digital Logic gates: VTC, NM and t PD 10 8 #9 Analog/Digital Conversion 11 9 Simulation of a CMOS two-input NAND gate using SPICE Design of an Experiment Pass Transistor Logic Gates Simulation of a TTL two-input NAND gate using SPICE

12 3. Homework schedule 3.1 Minimal Required Homework Problem set s15s_elct7.fm - 5 Numbers in the Problem Set Contents column of the following table refer to the problem designations in the course textbook; descriptions of other assignments/problems are posted on the course webpage. Set # #12 Analysis of the characteristic points on the BJT inverter VTC. 14 * in 4.2 calculate the capacitance per unit area, since the parameters L and W are not specified. The minimum required homework set is the result of a compromise made with the past generations of students who had complained that the double number of problems presented them with too much work. Current students willing to acquire a solid knowledge of the subject are strongly advised to solve twice as many problems, including those from past exams posted on the course homepage. 3.2 Policy on credit for homework assignments For full credit on problem solutions: 3.21 give answers to all questions, Problem Set Contents S emester week due #1 Analysis of problem areas in the exams of previous two semesters. 1 #2 2.2, 2.3, 2.7, 2.9, 2.12, 2.23, #3 2.45, 2.52, 3.1, 3.2, 3.8, 3.13, 3.18; bonus point, 3 #4 3.22, 3.26, 3.35, 3.43, 3.48, 3.51, 3.56, 4 #5 3.58, 3.66, 3.69, 3.71, 3.72, 3.73, #6 3.78, 3.83, 3.86, 3.92, 3.100(a), #7 4.2*, 4.4, 4.6, 4.8, 4.10, 4.15, #8 Analysis of the characteristic points on the CMOS inverter VTC. 9 #9 6.1, 6.2, 6.3, 6.7, 6.8, 6.9, #10 Calculation of I/O Parasitic Capacitances of the CMOS inverter circuit. 12 #11 5.1, 5.2, 5.4, 5.13, 5.31, 5.32, show the original and auxiliary circuit models with circuiit elements labelled by their parameters (which are not the parameter values), 3.23 indicate in the circuit model the positive reference directions of all voltages and currents which are involved in the solution process, 3.24 provide all symbolic and numerical expressions whose evaluation produces shown numerical results, 3.25 apply the determinant method for solving sets of simultaneous algebraic equations.

13 3.3Policy on submission of Homework Reports s15s_elct7.fm This policy promotes good planning habits. The fact that something went wrong the morning of the due day does not make a case for delaying the due time. We ought to be prepared for the day when something unusual happens All homework reports (solutions) are due at the beginning of the last class of the week In order to discourage the practice of preparing the reports during the time scheduled for classes, the absolute deadline for handing in the homework reports is five minutes after the time scheduled for the beginning of the class Homework reports handed in after the deadline, but before the beginning of the first class of the next week are accepted for half credit Homework reports are not considered turned in if they are not completly covered by a completely filled out cover sheet posted at the course webpage. 4. ABET Documentation 4.1 EAC and CAC Student Learning Objectives 1. Students will be able to apply the large signal method of analysis to electronic circuits that contain nonlinear circuit elements: diodes, FETs and BJTs. 2. Students will be able to apply the SPICE simulation method of analysis to electronic circuits that contain nonlinear circuit elements: diodes, FETs and BJTs. 3. Students will be able to design FET and BJT inverter circuits with a required noise margin and fanout, inverters of minimum size, with equal rise and fall times, and with specified logic threshold voltage value. 4. Students will be able to explain the tradeoffs for lowering power dissipation in digital electronic circuits. 5. Students will be able to analyse combinational logic circuits to determine the Boolean function implemented by the circuit, 6. Students will be able to design combinational static CMOS gates so that they implement a desired Boolean function, and to design the transistor aspect ratios so that the CMOS gate has the same rise and fall times as the reference inverter. 7. Students will be able to give examples of the three established principles of encoding the logic/ numeric values in memory cells: by the state of a bistable circuit, by an electrical charge on a capacitance, and by a FET s threshold voltage value. 8. Students will be able to state the challenges and the complexity tradeoffs in the design of modern memory arrays. 9. Students will be able to state the design principles used in legacy TTL and ECL integrated circuits.

14 s15s_elct7.fm Students will be able to conduct experiments in order to collect, analyze, and interpret data. 11. Students will be able to explain the properties of semiconductor materials and the mechanisms of charge transportation in semiconductor materials. 12. Students will be able to design an experiment to measure the propagation delay of a representative of two families of widely used digital logic gates (4xxx series CMOS and 74LSxx series TTL). 13. The student will be able to function effectively on a team with effectiveness being determined as documented in lab reports, instructor observations, and peer ratings. 4.2 ABET Outcomes Supported EAC CAC Outcome Supporting SLOs Outcome Supporting SLOs a 11 b 10, 12 c 3, 6 d 13 e 5 i 9 j 4, 7, 8 k 1, 2 No CAC outcomes are supported 4.3 ABET Description of EAC Outcomes a - b - c - d - e - i - j - k - An ability to apply knowledge of mathematics, science, and engineering. An ability to design and conduct experiments, as well as to analyze and interpret data. An ability to design a system, component, or process to meet desired needs within realistic constraints such as economic, environmental, social, political, ethical, health and safety, manufacturability, and sustainability. An ability to function on multidisciplinary teams. An ability to identify, formulate, and solve engineering problems. A recognition of the need for, and an ability to engage in life-long learning. A knowledge of contemporary issues. An ability to use the techniques, skills, and modern engineering tools necessary for engineering practice.

15 s15s_elct7.fm - 1 Electronics I The University of Toledo EECS Department EECS /005 CRN: Instructor: Anthony D. Johnson Class Location: PL anthony.johnson@utoledo.edu Class Day/Time: MWF/ 9:00 to 9:50 A.M. Office Hours: MWF 2:00-3:00 P.M. Lab Location: NE-1018 Office Location: NH-2049 Lab Day/Time: Please see the schedule on page 4. Office Phone: Credit Hours: 4 Term: Spring 2015 COURSE/CATALOG DESCRIPTION Large-signal and incremental characteristics of the pn diode, BJT, MOSFET and JFET. Large- signal analysis and computer simulation of devices and digital circuits. Logic gate implementation. Laboratory experiments and projects. STUDENT LEARNING OUTCOMES Student Learning Outcomes, as accepted by a vote of all program faculty, are listed on page 6. TEACHING STRATEGIES Face-to-face delivery of lectures and printed handouts are delivered in class. Homework set problems from the textbook, and Lab experiment assignments from the printed Lab Manual and postings on the course website (please see pages 5 and 4 of this syllabus) require written and computer generated reports. PREREQUISITES AND COREQUISITES One prerequisite course: EECS:2300 FOR LEVEL UG WITH MIN. GRADE OF D-. REQUIRED TEXTS AND ANCILLARY MATERIALS Bibliographic citation for the required course textbook is shown on page 3, and for the Lab manual on page 4. TECHNOLOGY REQUIREMENTS Hand held calculators/computers are allowed on examinations, but are not required. UNIVERSITY POLICIES (REQUIRED AS IS) Policy Statement on Non-Discrimination on the basis of Disability (ADA) The University is a equal opportunity educational institution. Please read The University s Policy Statement on Nondiscrimination on the Basis of Disability Americans with Disability Act Compliance.) ACADEMIC ACCOMODATIONS (REQUIRED AS IS) The University of Toledo is committed to providing equal access to education for all students. If you have a documented disability or you believe you have a disability and would like information regarding academic accommodations/adjustments in this course please contact the Student Disabiliti Services Office. ACADEMIC POLICIES Only advice not to miss the classes is offered. Professionals are expected to grow up at some time.

16 s15s_elct7.fm - 2 COURSE EXPECTATIONS In absence of a university wide policy on tardeness, students are let to enter the class room at any time - better late than never. No visits to restrooms are allowed during examination time. Policies on credit for Lab and homework reports are stated on pages 4 and 5 respectively; full credit on late reports is assigned only under exceptional circumstances. No extra credit. Attendance is taken only to encourage students to attend - it works. GRADING No weights are involved. Credit points are equal to percentages, since full credit for the course is 100 points. Distribution of points over Homeworks/Lab/Midterms/Final is given on page 3. Credits for Homework and Lab reports are provided one week after a report s due date. Credits for midterms are provided during the next class following the midterm. Midterm Grading Distribution of the midterms total numbers of points between three problems depends on the content of problems which is variable from semester to semester. Students performance on midterms shows whether they are studying during the whole semester. Final Grading Distribution of the final s total number of points between three problems depends on the content of problems which changes from semester to semester. COMMUNICATION GUIDELINES adresses and phone numbers of the instructor, and Lab assistants and graders are displayed on pages 3 and 4. STUDENT SUPPORT SERVICES Students with inadequate preparation in Mathematics and Physics can benefit from tutoring provided by the institution s academic and student support services. EECS department provides instructors and GAs office hours. COURSE SCHEDULE The course calendar by textbook topics per semester weeks is shown on page 3. Alignment of textbook topics with SLOs is not a straight forward matter for a number of reasons. Description of SLO assessment methods occupies a few pages in the ABET assessment report.

17 Electronics I s15s_elct7.fm - 3 SYLLABUS Week Starting Subject 1. January 12 Chapter 1 Introduction to Electronics Chapter 2 Solid State Electronics Materials 2. January 19 Chapter 3 Solid State Diodes 3. January 26 Chapter 3 Solid State Diode Circuits 4. February 2.Section 3.13 through 3.16 Rectifier circuits. 5. February 9 Chapter 4 Field Effect Transistors Midterm#1 6. February 16 Chapter 6 Introduction to Digital Electronics. 7. February 23 Chapter 7 Static CMOS: 7.1 and 7.2 CMOS Inverter circuit. 8. March 2 Chapter 7 : 7.2 CMOS Inverter circuit. Section 12.3 DAC and 12.4 ADC 9. March 16 Chapter 7 CMOS: 7.5 CMOS NAND and NOR Gates. 10. March 23 Chapter 7 CMOS: 7.6 through 7.10 Design of Complex gates March 30 Chapter 5 Bipolar Junction Transistor. Midterm#2 12. April 6 Chapter 5 Bipolar Junction Transistor. 13. April 13 BJT Inverter 14. April 20 Chapter 9 Bipolar Logic Circuits. 15. April 27 Chapter 8 MOS Memory and storage circuits. Objectivs Prerequisites Understanding the operation of electronic circuit components and their piecewise linear models. Introduction to basic digital circuits, and digital circuit families. Hands-on experience in simulation, test, and measurement of electronic circuits. For more detailed description please see Section 4. EECS 2300 Electric Circuits (with a grade of C or higher, if you want your instructor s advice). Textbook: Jaeger/Blalock: Microelectronic Circuit Design-4th Ed., McGraw-Hill, 2010, ISBN / Exam policy: Two Midterm Exams (of which the first missed midterm is optional), and a mandatory comprehensive Final examination in the final s week. Points for one missed midterm are transferred to the Final s point pool. Missed Final can be taken at the Final s place and time of any semester in which the course is offered. Missing all three examinations results in failing the course. Grading Policy: Homeworks / Lab / two Midterms / Final = 12/24/30/34. Instructor: Dr. A.D. Johnson; office NI-2049; phone x8176. Course webpage: Homework grader Ms, Jahnavi Yalamanchili, office: NE-2042, office hours: MW 11:00 to12.00pm, manchilis@gmail.com. Unless stated otherwise, location of graders office hours: NI-2000 South bridge between towers.

18 2. Lab information 2.1 Lab Room: NE Electronics Lab 2.2 Schedule of Lab Sessions 2.3 Schedule of Lab Assignments 2.4 Lab Assignments s15s_elct7.fm - 4 Section Time GA GA office GA s office hours 3400:002 M 3:00-5:200PM Sahu, Abhishek abhishek.sahu@rockets.utoledo.edu 3400:003 T 2:00-4:20PM Hazari, Noor Ahmad NoorAhmad.Hazari@rockets.utoledo.edu NE :004 W 3:00-5:20PM Sahu, Abhishek NE :005 F 11:00-01:20PM Hazari, Noor Ahmad Description of Experiments: #1 through #14 is provided in the Electronics Lab Manual I, by Dr. R.King, which is available from the campus bookstore. Descriptions of Lab Assignments #9 through #12 are posted on the course webpage. Prelab Assignment. To improve the ratio of the time spent building the experimental circuit on the protoboard to the time devoted to the educational experience through experiments on the built circuit, students are required to prepare (carries 25% of the grade) a good quality, computer generated drawing of the physical layout of circuits to be built. Lab report: Computer generated Lab reports are required for full credit. For details, please see the course webpage. Grading Policy: Prelab Assignment / Lab Experiment / Lab Report = 0.5 / 0.75 / MW 3.00 to 4.00PM NO Office MT to 12.00PM Experiment numbering in this schedule refers to the the Electronics Lab Manual I, by Dr. R.J.King. Semester Lab week Assignment Experiment 3 1 #1 Using the Digital Storage Oscilloscope 4 2 #3 Diodes 5 3 #11 DC Analysis of a Diode Circuit Using SPICE 6 4 #13 Simulation of a bridge rectifier using SPICE 7 5 #14 Diode Reverse Recovery as Observed using SPICE 8 6 #6 SPICE modelling of MOSFET and JFET 9 7 #7 Characterizing Digital Logic gates: VTC, NM and t PD 10 8 #9 Analog/Digital Conversion 11 9 Simulation of a CMOS two-input NAND gate using SPICE Design of an Experiment Pass Transistor Logic Gates Simulation of a TTL two-input NAND gate using SPICE

19 3. Homework schedule 3.1 Minimal Required Homework Problem set s15s_elct7.fm - 5 Numbers in the Problem Set Contents column of the following table refer to the problem designations in the course textbook; descriptions of other assignments/problems are posted on the course webpage. Set # #12 Analysis of the characteristic points on the BJT inverter VTC. 14 * in 4.2 calculate the capacitance per unit area, since the parameters L and W are not specified. The minimum required homework set is the result of a compromise made with the past generations of students who had complained that the double number of problems presented them with too much work. Current students willing to acquire a solid knowledge of the subject are strongly advised to solve twice as many problems, including those from past exams posted on the course homepage. 3.2 Policy on credit for homework assignments For full credit on problem solutions: 3.21 give answers to all questions, Problem Set Contents S emester week due #1 Analysis of problem areas in the exams of previous two semesters. 1 #2 2.2, 2.3, 2.7, 2.9, 2.12, 2.23, #3 2.45, 2.52, 3.1, 3.2, 3.8, 3.13, 3.18; bonus point, 3 #4 3.22, 3.26, 3.35, 3.43, 3.48, 3.51, 3.56, 4 #5 3.58, 3.66, 3.69, 3.71, 3.72, 3.73, #6 3.78, 3.83, 3.86, 3.92, 3.100(a), #7 4.2*, 4.4, 4.6, 4.8, 4.10, 4.15, #8 Analysis of the characteristic points on the CMOS inverter VTC. 9 #9 6.1, 6.2, 6.3, 6.7, 6.8, 6.9, #10 Calculation of I/O Parasitic Capacitances of the CMOS inverter circuit. 12 #11 5.1, 5.2, 5.4, 5.13, 5.31, 5.32, show the original and auxiliary circuit models with circuiit elements labelled by their parameters (which are not the parameter values), 3.23 indicate in the circuit model the positive reference directions of all voltages and currents which are involved in the solution process, 3.24 provide all symbolic and numerical expressions whose evaluation produces shown numerical results, 3.25 apply the determinant method for solving sets of simultaneous algebraic equations.

20 3.3Policy on submission of Homework Reports s15s_elct7.fm This policy promotes good planning habits. The fact that something went wrong the morning of the due day does not make a case for delaying the due time. We ought to be prepared for the day when something unusual happens All homework reports (solutions) are due at the beginning of the last class of the week In order to discourage the practice of preparing the reports during the time scheduled for classes, the absolute deadline for handing in the homework reports is five minutes after the time scheduled for the beginning of the class Homework reports handed in after the deadline, but before the beginning of the first class of the next week are accepted for half credit Homework reports are not considered turned in if they are not completly covered by a completely filled out cover sheet posted at the course webpage. 4. ABET Documentation 4.1 EAC and CAC Student Learning Objectives 1. Students will be able to apply the large signal method of analysis to electronic circuits that contain nonlinear circuit elements: diodes, FETs and BJTs. 2. Students will be able to apply the SPICE simulation method of analysis to electronic circuits that contain nonlinear circuit elements: diodes, FETs and BJTs. 3. Students will be able to design FET and BJT inverter circuits with a required noise margin and fanout, inverters of minimum size, with equal rise and fall times, and with specified logic threshold voltage value. 4. Students will be able to explain the tradeoffs for lowering power dissipation in digital electronic circuits. 5. Students will be able to analyse combinational logic circuits to determine the Boolean function implemented by the circuit, 6. Students will be able to design combinational static CMOS gates so that they implement a desired Boolean function, and to design the transistor aspect ratios so that the CMOS gate has the same rise and fall times as the reference inverter. 7. Students will be able to give examples of the three established principles of encoding the logic/ numeric values in memory cells: by the state of a bistable circuit, by an electrical charge on a capacitance, and by a FET s threshold voltage value. 8. Students will be able to state the challenges and the complexity tradeoffs in the design of modern memory arrays. 9. Students will be able to state the design principles used in legacy TTL and ECL integrated circuits.

21 s15s_elct7.fm Students will be able to conduct experiments in order to collect, analyze, and interpret data. 11. Students will be able to explain the properties of semiconductor materials and the mechanisms of charge transportation in semiconductor materials. 12. Students will be able to design an experiment to measure the propagation delay of a representative of two families of widely used digital logic gates (4xxx series CMOS and 74LSxx series TTL). 13. The student will be able to function effectively on a team with effectiveness being determined as documented in lab reports, instructor observations, and peer ratings. 4.2 ABET Outcomes Supported EAC CAC Outcome Supporting SLOs Outcome Supporting SLOs a 11 b 10, 12 c 3, 6 d 13 e 5 i 9 j 4, 7, 8 k 1, 2 No CAC outcomes are supported 4.3 ABET Description of EAC Outcomes a - b - c - d - e - i - j - k - An ability to apply knowledge of mathematics, science, and engineering. An ability to design and conduct experiments, as well as to analyze and interpret data. An ability to design a system, component, or process to meet desired needs within realistic constraints such as economic, environmental, social, political, ethical, health and safety, manufacturability, and sustainability. An ability to function on multidisciplinary teams. An ability to identify, formulate, and solve engineering problems. A recognition of the need for, and an ability to engage in life-long learning. A knowledge of contemporary issues. An ability to use the techniques, skills, and modern engineering tools necessary for engineering practice.

22 s15s_elct7.fm - 1 Electronics I The University of Toledo EECS Department EECS /005 CRN: Instructor: Anthony D. Johnson Class Location: PL anthony.johnson@utoledo.edu Class Day/Time: MWF/ 9:00 to 9:50 A.M. Office Hours: MWF 2:00-3:00 P.M. Lab Location: NE-1018 Office Location: NH-2049 Lab Day/Time: Please see the schedule on page 4. Office Phone: Credit Hours: 4 Term: Spring 2015 COURSE/CATALOG DESCRIPTION Large-signal and incremental characteristics of the pn diode, BJT, MOSFET and JFET. Large- signal analysis and computer simulation of devices and digital circuits. Logic gate implementation. Laboratory experiments and projects. STUDENT LEARNING OUTCOMES Student Learning Outcomes, as accepted by a vote of all program faculty, are listed on page 6. TEACHING STRATEGIES Face-to-face delivery of lectures and printed handouts are delivered in class. Homework set problems from the textbook, and Lab experiment assignments from the printed Lab Manual and postings on the course website (please see pages 5 and 4 of this syllabus) require written and computer generated reports. PREREQUISITES AND COREQUISITES One prerequisite course: EECS:2300 FOR LEVEL UG WITH MIN. GRADE OF D-. REQUIRED TEXTS AND ANCILLARY MATERIALS Bibliographic citation for the required course textbook is shown on page 3, and for the Lab manual on page 4. TECHNOLOGY REQUIREMENTS Hand held calculators/computers are allowed on examinations, but are not required. UNIVERSITY POLICIES (REQUIRED AS IS) Policy Statement on Non-Discrimination on the basis of Disability (ADA) The University is a equal opportunity educational institution. Please read The University s Policy Statement on Nondiscrimination on the Basis of Disability Americans with Disability Act Compliance.) ACADEMIC ACCOMODATIONS (REQUIRED AS IS) The University of Toledo is committed to providing equal access to education for all students. If you have a documented disability or you believe you have a disability and would like information regarding academic accommodations/adjustments in this course please contact the Student Disabiliti Services Office. ACADEMIC POLICIES Only advice not to miss the classes is offered. Professionals are expected to grow up at some time.

23 s15s_elct7.fm - 2 COURSE EXPECTATIONS In absence of a university wide policy on tardeness, students are let to enter the class room at any time - better late than never. No visits to restrooms are allowed during examination time. Policies on credit for Lab and homework reports are stated on pages 4 and 5 respectively; full credit on late reports is assigned only under exceptional circumstances. No extra credit. Attendance is taken only to encourage students to attend - it works. GRADING No weights are involved. Credit points are equal to percentages, since full credit for the course is 100 points. Distribution of points over Homeworks/Lab/Midterms/Final is given on page 3. Credits for Homework and Lab reports are provided one week after a report s due date. Credits for midterms are provided during the next class following the midterm. Midterm Grading Distribution of the midterms total numbers of points between three problems depends on the content of problems which is variable from semester to semester. Students performance on midterms shows whether they are studying during the whole semester. Final Grading Distribution of the final s total number of points between three problems depends on the content of problems which changes from semester to semester. COMMUNICATION GUIDELINES adresses and phone numbers of the instructor, and Lab assistants and graders are displayed on pages 3 and 4. STUDENT SUPPORT SERVICES Students with inadequate preparation in Mathematics and Physics can benefit from tutoring provided by the institution s academic and student support services. EECS department provides instructors and GAs office hours. COURSE SCHEDULE The course calendar by textbook topics per semester weeks is shown on page 3. Alignment of textbook topics with SLOs is not a straight forward matter for a number of reasons. Description of SLO assessment methods occupies a few pages in the ABET assessment report.

24 Electronics I s15s_elct7.fm - 3 SYLLABUS Week Starting Subject 1. January 12 Chapter 1 Introduction to Electronics Chapter 2 Solid State Electronics Materials 2. January 19 Chapter 3 Solid State Diodes 3. January 26 Chapter 3 Solid State Diode Circuits 4. February 2.Section 3.13 through 3.16 Rectifier circuits. 5. February 9 Chapter 4 Field Effect Transistors Midterm#1 6. February 16 Chapter 6 Introduction to Digital Electronics. 7. February 23 Chapter 7 Static CMOS: 7.1 and 7.2 CMOS Inverter circuit. 8. March 2 Chapter 7 : 7.2 CMOS Inverter circuit. Section 12.3 DAC and 12.4 ADC 9. March 16 Chapter 7 CMOS: 7.5 CMOS NAND and NOR Gates. 10. March 23 Chapter 7 CMOS: 7.6 through 7.10 Design of Complex gates March 30 Chapter 5 Bipolar Junction Transistor. Midterm#2 12. April 6 Chapter 5 Bipolar Junction Transistor. 13. April 13 BJT Inverter 14. April 20 Chapter 9 Bipolar Logic Circuits. 15. April 27 Chapter 8 MOS Memory and storage circuits. Objectivs Prerequisites Understanding the operation of electronic circuit components and their piecewise linear models. Introduction to basic digital circuits, and digital circuit families. Hands-on experience in simulation, test, and measurement of electronic circuits. For more detailed description please see Section 4. EECS 2300 Electric Circuits (with a grade of C or higher, if you want your instructor s advice). Textbook: Jaeger/Blalock: Microelectronic Circuit Design-4th Ed., McGraw-Hill, 2010, ISBN / Exam policy: Two Midterm Exams (of which the first missed midterm is optional), and a mandatory comprehensive Final examination in the final s week. Points for one missed midterm are transferred to the Final s point pool. Missed Final can be taken at the Final s place and time of any semester in which the course is offered. Missing all three examinations results in failing the course. Grading Policy: Homeworks / Lab / two Midterms / Final = 12/24/30/34. Instructor: Dr. A.D. Johnson; office NI-2049; phone x8176. Course webpage: Homework grader Ms, Jahnavi Yalamanchili, office: NE-2042, office hours: MW 11:00 to12.00pm, manchilis@gmail.com. Unless stated otherwise, location of graders office hours: NI-2000 South bridge between towers.