Lecture Notes in Computer Science 7606

Transcription

1 Lecture Notes in Computer Science 7606 Commenced Publication in 1973 Founding and Former Series Editors: Gerhard Goos, Juris Hartmanis, and Jan van Leeuwen Editorial Board David Hutchison Lancaster University, UK Takeo Kanade Carnegie Mellon University, Pittsburgh, PA, USA Josef Kittler University of Surrey, Guildford, UK Jon M. Kleinberg Cornell University, Ithaca, NY, USA Alfred Kobsa University of California, Irvine, CA, USA Friedemann Mattern ETH Zurich, Switzerland John C. Mitchell Stanford University, CA, USA Moni Naor Weizmann Institute of Science, Rehovot, Israel Oscar Nierstrasz University of Bern, Switzerland C. Pandu Rangan Indian Institute of Technology, Madras, India Bernhard Steffen TU Dortmund University, Germany Madhu Sudan Microsoft Research, Cambridge, MA, USA Demetri Terzopoulos University of California, Los Angeles, CA, USA Doug Tygar University of California, Berkeley, CA, USA Gerhard Weikum Max Planck Institute for Informatics, Saarbruecken, Germany

2 José L. Ayala Delong Shang Alex Yakovlev (Eds.) Integrated Circuit and System Design Power and Timing Modeling, Optimization and Simulation 22nd International Workshop, PATMOS 2012 Newcastle upon Tyne, UK, September 4-6, 2012 Revised Selected Papers 13

3 Volume Editors José L. Ayala Complutense University of Madrid Facultad de Informática, Madrid, Spain Delong Shang Newcastle University School of Electronic Engineering Newcastle upon Tyne, NE1 7RU, UK Alex Yakovlev Newcastle University School of Electronic Engineering Newcastle upon Tyne, NE1 7RU, UK ISSN e-issn ISBN e-isbn DOI / Springer Heidelberg Dordrecht London New York Library of Congress Control Number: CR Subject Classification (1998): C.4, I.6.3-7, C.2, B.5.2, B.6.3, B.7.2, D.3.4 LNCS Sublibrary: SL 1 Theoretical Computer Science and General Issues Springer-Verlag Berlin Heidelberg 2013 This work is subject to copyright. All rights are reserved, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, re-use of illustrations, recitation, broadcasting, reproduction on microfilms or in any other way, and storage in data banks. Duplication of this publication or parts thereof is permitted only under the provisions of the German Copyright Law of September 9, 1965, in its current version, and permission for use must always be obtained from Springer. Violations are liable to prosecution under the German Copyright Law. The use of general descriptive names, registered names, trademarks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. Typesetting: Camera-ready by author, data conversion by Scientific Publishing Services, Chennai, India Printed on acid-free paper Springer is part of Springer Science+Business Media (

4 Preface PATMOS 2012 was the 22nd in a series of international workshops on Power and Timing Modeling, Optimization and Simulation. The PATMOS meeting has evolved, during the years, into a leading scientific event where industry and academia meet to discuss power and timing aspects in modern integrated circuit and system design. Both universities and companies are invited to participate. The objective of this workshop is to provide a forum in which to discuss and investigate emerging challenges in methodologies and tools for the design of upcoming generations of integrated circuits and systems, including reconfigurable hardware such as FPGAs. The technical program focused on timing, performance, and power consumption as well as architectural aspects with particular emphasis on modeling, design, characterization, analysis, and optimization. September 2012 Alex Yakovlev Delong Shang

5 Organization PATMOS 2012 was organized by Newcastle University, UK. Organizing Committee General Chairs Alex Yakovlev Delong Shang Newcastle University, UK Newcastle University, UK Program Chair José L. Ayala UCM, Spain Publicity Chair Ian Clark Newcastle University, UK Publication Chair Fei Xia Newcastle University, UK Local Committee Joan Atkinson Maciej Koutny Claire Smith Danil Sokolov Steering Committee Antonio J. Acosta Nadien Azemard Joan Figueras Reiner Hartenstein Jorge Juan-Chico Sponsoring Institutions Enrico Macii Philipe Maurien Jose Monteiro Wolfgang Nebel Vassilis Paliouras Christian Piguet Dimitrios Soudris Diederik Verkest Roberto Zafalon Newcastle University University of Leicester EPSRC Formal Methods Europe

6 Table of Contents Sleep-Transistor Based Power-Gating Tradeoff Analyses... 1 Sven Rosinger and Wolfgang Nebel Modelling and Analysis of Manufacturing Variability Effects from Process to Architectural Level Chenxi Ni, Ziyad Al Tarawneh, Gordon Russell, and Alex Bystrov Non-invasive Power Simulation at System-Level with SystemC Daniel Lorenz, Philipp A. Hartmann, Kim Grüttner, and Wolfgang Nebel A Standard Cell Optimization Method for Near-Threshold Voltage Operations Masahiro Kondo, Shinichi Nishizawa, Tohru Ishihara, and Hidetoshi Onodera An Extended Metastability Simulation Method for Synchronizer Characterization Salomon Beer and Ran Ginosar Phase Space Based NBTI Model Reef Eilers, Malte Metzdorf, Sven Rosinger, Domenik Helms, and Wolfgang Nebel Fast Propagation of Hamming and Signal Distances for Register-Transfer Level Datapaths Axel Reimer, Lars Kosmann, Daniel Lorenz, and Wolfgang Nebel Noise Margin Based Library Optimization Considering Variability in Sub-threshold Tobias Gemmeke, Maryam Ashouei, and Tobias G. Noll TCP Window Based DVFS for Low Power Network Controller SoC Eyal-Itzhak Nave and Ran Ginosar Adaptive Synchronization for DVFS Applications Ghaith Tarawneh and Alex Yakovlev Muller C-Element Metastability Containment Thomas Polzer, Andreas Steininger, and Jakob Lechner

7 VIII Table of Contents Low Power Implementation of Trivium Stream Cipher J.M. Mora-Gutiérrez, C.J. Jiménez-Fernández, and M. Valencia-Barrero A Generic Architecture for Robust Asynchronous Communication Links Jakob Lechner and Robert Najvirt Direct Statistical Simulation of Timing Properties in Sequential Circuits Javier Rodríguez, Qin Tang, Amir Zjajo, Michel Berkelaar, and Nick van der Meijs PVTA Tolerant Self-adaptive Clock Generation Architecture Jordi Pérez-Puigdemont, Antonio Calomarde, and Francesc Moll On-Chip NBTI and PBTI Tracking through an All-Digital Aging Monitor Architecture Hossein Karimiyan Alidash, Andrea Calimera, Alberto Macii, Enrico Macii, and Massimo Poncino Two-Phase MOBILE Interconnection Schemes for Ultra-Grain Pipeline Applications Juan Núñez, María J. Avedillo, and José M.Quintana Design of a 150 mv Supply, 2 MIPS, 90nm CMOS, Ultra-Low-Power Microprocessor Pieter Weckx, Nele Reynders, Ilse de Moffarts, and Wim Dehaene Run-Time Measurement of Harvested Energy for Autarkic Sensor Operation Dimitris Bekiaris, Ioannis Kosmadakis, George Stassinopoulos, Dimitrios Soudris, Theodoros Laopoulos, Gregory Doumenis, and Stylianos Siskos Low-Power Delay Sensors on FPGAs Panagiotis Sakellariou and Vassilis Paliouras Observability Conditions and Automatic Operand-Isolation in High-Throughput Asynchronous Pipelines Arash Saifhashemi and Peter A. Beerel Dynamic Power Management of a Computer with Self Power-Managed Components Maryam Triki, Yanzhi Wang, Ahmed C. Ammari, and Massoud Pedram Network Time Synchronization: A Full Hardware Approach Jorge Juan, Julian Viejo, and Manuel J. Bellido

8 Table of Contents IX Case Studies of Logical Computation on Stochastic Bit Streams Peng Li, Weikang Qian, David J. Lilja, Kia Bazargan, and Marc D. Riedel drail: A Novel Physical Layout Methodology for Power Gated Circuits Jatin N. Mistry, John Biggs, James Myers, Bashir M. Al-Hashimi, and David Flynn Author Index