Yiyu Shi Employment Missouri University of Science and Technology 09/2010 - Formerly Univeresity of Missouri, Rolla, Rolla, MO, US Assistant Professor in Electrical and Computer Engineering Dept. Carnegie Mellon University 12/2009-04/2010 Pittsburgh, PA, US Postdoctoral Researcher in Electrical and Computer Engineering Dept. Education University of California, Los Angeles 09/2007-06/2009 Los Angeles, CA, US Doctor of Philosophy in Electrical Engineering Dissertation: Modeling and Optimization for Power Integrity Considering the Uncertainties of VLSI Circuits and Systems University of California, Los Angeles 08/2005-09/2007 Los Angeles, CA, US Master of Science in Electrical Engineering Tsinghua University 09/2001-07/2005 Beijing, P.R. China Bachelor of Engineering in Electrical Engineering Research Interests Professional Activities VLSI design automation 3D IC Renewable energy Member of IEEE (Institute of Electrical and Electronics Engineers, Inc), SRC (Semiconductor Research Corporation) and SIAM (Society for Industrial and Applied Mathematics) Technical Program Committee Member, International Symosium on Physical Design (2011), International Symposium on VLSI Design, Automation and Test (2011). Invited Reviewer of IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, IEEE Transactions on Very Large Scale Integration Systems, IEEE Transactions on Circuits and Systems I, IEEE Transactions on Circuits and Systems II, ACM Transactions on Design Automation of Electronic Systems Invited Reviewer of Design Automation Conference and International Conference on Computer-Aided Design Courses Taught CpE 311, Introduction to VLSI design, Fall 2010
Patents Selected Publication Yiyu Shi, Jinjun Xiong, Chandu Visweswariah and Vladimir Zolotov, System and Method for Multilayer Process Space Coverage and Path Selection for Atspeed Testing, IBM Disclosure #YOR820080853, (US Patent Pending) Books and Book Chapters B1. Yiyu Shi, Hao Yu and Lei He, Noise Driven In Package Decoupling Capacitor Optimization for Power Integrity, chapter in Recent Advancements in Modeling of Semiconductor Processes, Circuits and Chip-Level Interactions, edited by Rasit Onur Topaloglu and Peng Li, Bentham Publishing 2010 (in press). B2. Yiyu Shi, Jinjun Xiong and Lei He, Stochastic Optimization on Correlated Data Set, chapter in Stochastic Optimization, Theory and Applications, Intech publishing 2010 (in progress). Journal articles J1. Yiyu Shi, Bike Xie, and Yanjie Mao, Circuit Simulation Method in Mathematical Modeling, Chinese Journal of Engineering Mathematics, 21(7): 43-48, 2004. (In Chinese) J2. Yiyu Shi, Paul Mesa, Hao Yu and Lei He, Circuit Simulated Obstacle-aware Steiner Routing, ACM Transaction on Design Automation of Electronic Systems (TODAES), 12(3), 2007. J3. Hao Yu, Yiyu Shi and Lei He, Thermal Via Allocation for 3D ICs Considering Temporally and Spatially Variant Thermal Power, IEEE Transactions on Very Large Scale Integration Systems, 16(12): 1609-1619, 2008 J4. Yiyu Shi, Jinjun Xiong, Chunchen Liu and and Lei He, Efficient Decoupling Capacitance Budgeting Considering Operation and Process Variations, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 27(7): 1253-1263, 2008. J5. Yiyu Shi and Lei He, EMPIRE: An Efficient and Compact Multiple-Parameterized Model Order Reduction Method for Physical Optimization, IEEE Transactions on Very Large Scale Integration Systems, 2009 (in press). J6. Hao Yu, Chunta Chu, Yiyu Shi, David Smart, Lei He and Sheldon X.D. Tan, Fast Analysis of Large Scale Inductive Interconnect by Block Structure Preserved Macromodeling, IEEE Transactions on Very Large Scale Integration Systems, 2009 (in press). J7. Yiyu Shi, Jinjun Xiong, Howard Chen and Lei He, Runtime Resonance Noise Reduction with Current Prediction Enabled Frequency Actuator, IEEE Transactions on Very Large Scale Integration Systems, 2010 (in press). J8. Wei Yao, Yiyu Shi, Lei He and Sudhakar Pamarti, Worst-Case Estimation for Data-Dependent Timing Jitter and Amplitude Noise in High-Speed Differential Link, IEEE Transactions on Very Large Scale Integration Systems, 2009 (revised) Conference papers
C1. Yiyu Shi, Tong Jing, Lei He and Zhe Feng, CDCTree: Novel Obstacle-Avoiding Routing Tree Construction based on Current Driven Circuit Model. In: Proc. of Asia and South Pacific Design Automation Conference, 2006 (IEEE/ACM ASPDAC 06), Japan, pp.630-635. C2. Zhen Cao, Tong Jing, Yu Hu, Yiyu Shi, Xianlong Hong, Xiaodong Hu, and Guiying Yan, DraXRouter: Global Routing in X-Architecture with Dynamic Resource Assignment. In: Proc. of Asia and South Pacific Design Automation Conference, 2006 (IEEE/ACM ASPDAC 06), Japan, pp.618-623. C3. Yiyu Shi, Hao Yu, and Lei He, SAMSON: A Generalized Second-Order Arnoldi Method for Reducing Multiple Source Linear Network with Susceptance. In: Proc. of International Symposium on Physical Design, 2006 (IEEE/ACM ISPD 06), San Jose, pp. 25-32. C4. Yiyu Shi, Paul Mesa, Hao Yu and Lei He, Circuit Simulation Based Obstacleaware Steiner Routing. In: Proc. of Design Automation Conference (IEEE/ACM DAC 06), 2006, San Francisco, pp. 385-388 (Ranked 2nd among all physical design papers). C5. Hao Yu, Yiyu Shi and Lei He, Fast Analysis of Structured Power Grid by Triangularization Based Structure Preserving Model Order Reduction. In: Proc. of Design Automation Conference, 2006 IEEE/ACM DAC 06, San Francisco, pp. 205-210. C6. Hao Yu, Yiyu Shi, Lei He and Tanay Karnik, A Hotspot-Driven Thermal Via Allocation for 3D ICs by Parameterized Sensitivity, In: Proc. of International Symposium on Low Power Electronics and Design, 2006 (IEEE ISLPED 06), Germany, pp. 156-161. C7. Hao Yu, Yiyu Shi and Lei He, A Fast Block Structure Preserving Model Order Reduction with Inversed Inductance, In: Proc. of International Conf. on Computer- Aided Design, 2006 (IEEE/ACM ICCAD 06), San Jose, pp. 7-12. C8. Yiyu Shi and Lei He. EMPIRE: An Efficient and Compact Multiple-Parameterized Model Order Reduction Method for Physical Optimization, In: Proc. of International Symposium on Physical Design, 2007 (IEEE/ACM ISPD 07), Texas, pp. 51-58. C9. Yiyu Shi and Lei He. EMPIRE: An Efficient and Compact Multiple-Parameterized Model Order Reduction Method for Physical Optimization, the SRC Techcon Conference, 2007, Texas. C10. Yiyu Shi, Jinjun Xiong, Chunchen Liu and Lei He. Efficient Decoupling Capacitance Budgeting Considering Operation and Process Variations, In: Proc. of International Conf. on Computer-Aided Design, 2007 (IEEE/ACM ICCAD 07), San Jose, pp. 803-810. (Nominated for Best Paper Award) C11. Chunchen Liu, Junjie Su and Yiyu Shi, Temperature Aware routing Synthesis Considering Spatiotemporal Hotspot, In: Proc. of International Conf. on Compute Design, 2008 (IEEE/ACM ICCD 08), Lake Tahoe, pp. 107-113.(Nominated for Best Paper Award) C12. Yiyu Shi and Lei He, Scalable Symbolic Model Order Reduction, In Proc. of In-
ternational Behavioral Modeling and Simulation Conference, 2008 (IEEE BMAS 08), San Jose, pp. 112-117. C13. Yiyu Shi, Jinjun Xiong, Howard Chen and Lei He, Clock Frequency Actuator with Efficient Stochastic Current Prediction for Runtime Resonance Noise Reduction, In: Proc. of Asian and South Pacific Design Automation Conference, 2009 (IEEE/ACM ASPDAC 09), Japan, pp. 373-378. (Nominated for Best Paper Award) C14. Yiyu Shi, Wei Yao, Jinjun Xiong and Lei He, Incremental and On-demand Random Walk for Iterative Power Distribution Network Analysis, In: Proc. of Asian and South Pacific Design Automation Conference, 2009 (IEEE/ACM ASPDAC 09), Japan, pp. 185-190. C15. Wei Yao, Yiyu Shi and Lei He and Sudhakar Pamarti, Worst Case Timing Jitter and Amplitude Noise in Differential Signaling, accepted by International Symposium on Quality Electronic Design, 2009 (IEEE ISQED 09), San Jose. C16. Jinjun Xiong, Yiyu Shi, Vladimir Zolotov and Chandu Visweswariah, Statistical Multilayer Process Space Coverage for At-Speed Test, accepted by Design Automation Conference, 2009 (IEEE/ACM DAC 09), San Francisco (Nominated for Best Paper Award). C17. Jinjun Xiong, Yiyu Shi, Vladimir Zolotov and Chandu Visweswariah, Statistical Multilayer Process Space Coverage for At-Speed Test, accepted by International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Austin, 2009 (ACM Tau 09). C18. Wei Yao, Yiyu Shi and Lei He and Sudhakar Pamarti, Worst Case Timing Jitter and Amplitude Noise in Differential Signaling, SRC Techcon Conference, Texas, 2009. C19. Yiyu Shi, Wei Yao, Lei He and Sudhakar Pamarti, Joint Design-time and Post-silicon Optimization for Analog Circuits: A Case Study Using A High-speed Transmitter, SRC Techcon Conference, Texas, 2009 C20. Wei Yao, Yiyu Shi, Lei He and Sudhakar Pamarti, Joint Design-time and Postsilicon Optimization for Digitally Tuned Analog Circuits, accepted by International Conference on Computer-aided Design, San Jose, 2009 (IEEE/ACM ICCAD 09). C21. Jinjun Xiong, Yiyu Shi, Vladimir Zolotov and Chandu Visweswariah, Pre- ATPG Path Selection for Near Optimal Post-ATPG Process Space Coverage, accepted by International Conference on Computer-aided Design, San Jose, 2009 (IEEE/ACM ICCAD 09). C22. Bingjun Xiao, Yiyu Shi and Lei He, A Universal State-of-Charge Algorithm for Batteries,accepted by Design Automation Conference, 2010 (IEEE/ACM DAC 10). C23. Fang Gong, Hao Yu, Yiyu Shi and Lei He, QuickYield: An Efficient Non- Iterative Parametric Yield Estimation with Performance Constraints, accepted by Design Automation Conference, 2010 (IEEE/ACM DAC 10) Posters
P1. Yiyu Shi, Modeling and Optimization for Power Integrity Considering the Uncertainties of VLSI Circuits and Systems, 12th ACM/SIGDA Ph.D. Forum at Design Automation Conference, 2009. Invited Talks T1. Mixed Mode Statistical Timing Analysis, IBM CMOS Forum, 08/2007. T2. Multi-layer Process Space Coverage for At-Speed Testing, IBM CMOS Forum, 09/2008. T3. Statistical Load Current Profiling for Power Integrity Driven Design Methodologies, Texas A&M University, College Station, Texas, 10/2009. T4. Robust System Design in a Statistical World: Live Free, Die Hard, Missouri University of Science and Technology, 03/2010. T5. Robust System Design in a Statistical World: Live Free, Die Hard, University of Alberta, 03/2010. T6. Robust System Design in a Statistical World: Live Free, Die Hard, Texas Tech University, 04/2010. T7. Thermal/Power/Signal Co-Design for 3D Integrated Circuits, Industrial Technology Research Institute (ITRI), Taiwan, 09/2010. Short Courses C1. 2010 Short Courses for 3D IC Design, Modeling and Optimization, sponsored by IEEE CASS Taipei Chapter and Natoinal Tsinghua University, Taiwan, 09/06/2010-09/08/2010. Recent Honors DAC Alumni Scholarship 2010 Best Paper Award Finalist at Design Automation Conference 2009 IBM Invention Achievement Award for First Patent Application 2009 IBM Phd Fellowship Finalist 2009 Best Paper Award Finalist at Asian and South Pacific Design Automation Conference 2009 Best Paper Award Finalist at International Conference on Computer Design 2008 Department Outstanding M.S. Student 2007 IEEE/ACM William J. McCalla Best Paper Award Finalist at International Conference on Computer Aided Design 2007 Best Paper Award Finalist at Design Automation Conference 2006 UCLA University Fellowship 2005-2006 Rank 1/164 for overall undergraduate GPA in the Electrical Engineering Dept., Tsinghua University Outstanding Graduate Student in Beijing (top 0.5%) 2005 Outstanding Graduate Student in Tsinghua University (top 2%) 2005 Outstanding Bachelor Thesis in Tsinghua University (top 5%) 2005 Meritorious (First Prize) for the International Mathematical Contest in Modeling (MCM) 2005 Jiang Nanxiang Outstanding Performance Scholarship (top 0.2%) 2004
First Prize for the Chinese Undergraduate Mathematical Contest in Modeling (CUMCM) 2004 Honorable Mention (Second Prize) for the International Interdisciplinary Contest in Modeling (ICM) 2004 First Prize in Beijing for the Chinese Undergraduate Mathematical Contest in Modeling (CUMCM) 2003 Sumsung Outstanding Performance Scholarship 2003 Third Prize of Outstanding Academic Performance Scholarship 2003