A Report on Two-Day State Level Workshop on Digital System Design Using VHDL on CPLD board on 10th and 11th February 2012 Jointly organized by Virtual Labs (Electronics), IIT, Bombay and Progressive Education Society s MODERN COLLEGE OF ARTS SCIENCE & COMMERCE Shivajinagar, Pune-411005 DEPARTMENT OF ELECTRONIC SCIENCE
REPORT Department of Electronic Science of P.E. Society s Modern College of Arts, Science and Commerce, Pune-41105, and E-prayog, Virtual Lab (Electronics), IIT Bombay successfully organized two day State Level Workshop on Digital System Design using VHDL on CPLD Board on 10 th and 11th February 2012. In the workshop, 20 faculty members and 48 M.Sc. students from different regions of Maharashtra like Nagpur, Amravati, Nashik, Ahmadnagar, Mumbai, Satara, Sangali and Pune had participated. Inauguration : Workshop was inaugurated by Dr. M. B. Patil (IIT, Bombay) along with Dr. K.C. Mohite (Dean Science faculty, University of Pune), Dr. G.R.Ekbote, Chairman Business Council P.E. Society, Dr. P.B. Buchade (Chairman, BOS, Electronic Science), Dr.A.D.Shaligram (Head, Department of Electronic Science, University of Pune), Principal Dr. R.S. Zunjarrao, Prof S. R. Chaudhari (Vice Principal and Head, Department of Electronic Science), Mr. Abhishak Kamath (Virtual Lab, IIT Bombay), Prof. D.B.Gaikwad(Organizing Secretary) and G.M Tarate(Co-Ordinator). In this program, P.G. Department of Electronic Science, P.E. Society s Modern College of Arts, Science and Commerce, Pune-5, was declared as Excellent Nodal Centre for Virtual Labs (Electronics) IIT, Bombay. The aim of workshop was to give the participants hands on experience with a process of reconfigurable logic design, implementation and verification of logic systems using modern design tools of digital logic design using an affordable CPLD board designed by E-prayog, Virtual lab. During the workshop Dr. M. B. Patil, Dr.A.D.Shaligram, Mr. Abhishek Kamath, Prof D.B.Gaikwad delivered lectures explaining Virtual Lab, reconfigurable hardware, CPLD architecture, CPLD board uses and VHDL programming. Publication of lab manuals specially prepared for two days state level workshop on Digital system design using VHDL on CPLD board. Prof.G.M.Tarate, Prof.S.R.Chaudhari, Dr.A.D.Shaligram, Principal Dr.R.S. Zunjarrao, Dr.M.B.Patil(IIT,Powai), Prof.U.N.Kothavade, Prof.D.B.Gaikw
In the laboratory sessions M.Sc. Electronic Science (Part-II) under the guidance of Prof.U.N.Kothavade conducted practicals. They demonstrated applications of CPLD such as Robot, Real Time Clock developed using Helium board. During the workshop Dr.A.K.Walunj (Member of Management Council, University of Pune), Dr. R.K.Kamat (Reader, DOES, Shivaji University, Kolhapur), Dr. J.S. Kaddvarmath (Reader, DOES, Dharwad University,Karnataka ),Dr. D.C.Gharpure and Dr. M.S.Zambre (BOS Member, Electronic Science, University of Pune), Prof. Madhav Kube(Scientist E, DIAT, Pune ), Prof J.V.Khedkar(HOD.DOES, Fergusson College), Prof Z.B.Pathan (HOD.DOES, Poona College), Mr. Kiran Kale (Sr. ASIC Engineer, QLogic Pvt Ltd), Mr. Ganesh Shinde(Sr. Design Engineer, e-infochip), Mr. Vikram Gaikwad (Sr. Software Engineer,Wipro) EPM3064 based CPLD board and PIC 18F4550 based microcontroller board were distributed to all participating institutes. Lab manuals and peripheral boards prepared by Modern College were used in the workshop. During Valedictory function Dr. Tansen Chaudhari,(Fluid Control Pvt. Ltd.) expressed his thoughts on research and intellectual property rights. On this occasion Dr. Gajanan Ekbote, Chairman Business Council, P.E society, Prof. Jostna Ekbote, Prof. Padamakar Chirputkar, Dr. Arvind Pande, Principal Dr. R. S. Zunjarrao and Prof. S.S. Deshmukh, Vice principal and Secretary of P.E. Society were present. Dr.M.B.Patil explaining the features of Virtual Lab, IIT, Bombay Use of CPLD Board 1. These CPLD boards are useful for students of M.Sc. Electronics / Electronic Science / Applied Electronics/ Electronic Science Courses in Maharashtra and T.Y.B.Sc Electronic Science course of Pune University. 2. In the syllabus of M.Sc. Electronic Science (University of Pune), there is a theory paper Digital System design uses VHDL and eight practicals based on this theory paper. In this course, we are using these boards along with peripheral boards developed in our College.
3. M.Sc. students are using one board as a programmer in their project. Two Students are working on CPLD based projects such as Robot Design and Real time Clock.They may require device with more I/O and Macro cells.
Boards Used in the Workshop
Mr. Abhishek Kamath explaining practical to participants in the workshop Prof. D.B.Gaikwad explaining peripheral board Participants performing practicals List of participants
Sr. Name Of The Participant No. 1 Dr. Sangita Joshi College /Institute S. G. G. S. I.Eng.Tchhnology, Nanded 2 Dr. V.S.Kale KTHM College, Nashik 3 Dr. Satish Sharma RTM Nagpur University, Nagpur 4 Dr.P.B. Buchade Garware College, Pune-411004 5 Prof. Ansari Faheem Ahamad Poona College, Pune-411001 6 Prof Ansari Sajid Naeem Poona College, Pune-411001 7 Prof. Sneha Revankar Fr.C.Rodrigues inst. of Tecnology Mumbai 8 Prof. Preeti karpe Arts, Science & Commerce College, Nagar 9 Prof. M.B.WATH 10 Prof. Vijaya Jadkar Wadia College,Pune-411001 11 Prof Dhavale Sandip 12 Prof. N.S.HARANE 13 Prof Mallikarjun Hanamane Smt. Kasturbai College, Sangali 14 Prof Rajuskar R.S. Garware College, Pune-411004 15 Prof. Ranjana. Tilekar/Ubale 16 Prof Kamble P.B 17 prof. Soman Handge LVH College, Nashik 18 Mr. Jayaji Wankade 19 Mr. TANMAY MUTKURE 20 Mr. SAURABH YADGIRE 21 Mr. SWAPNIL SHELKE 22 Mr.GAJANAN RAUT 23 Mr. PARVEJ SAUDAGAR 24 Ms. AMITA TEMBHARE 25 Ms. ANUJA GUPTA 26 Ms. SNEHA INGALE 27 Ms. MADHAVI PACHPOR 28 Ms. POOJA MISHRA 29 Ms. RENUKA SHENDE 30 Ms. Mrunali A. Sherekar 31 Ms. Nimse S.S. 32 Ms. Bilra G.R 33 Ms. Dhage N.N 34 Ms. Anagha Bakare 35 Ms.Roshani Poduval 36 Mr.Siamak Mirshahi DOES, University Of Pune
37 Mr.Hani Masoumi DOES, University Of Pune 38 Mr. Santosh Jagtap 39 Mr. Bhavin Upadhyay Modern college, Pune-5 40 Mr. Rupesh Khatpe Modern college, Pune-5 41 Mr. Shashank Longhi 42 Mr. Gajanan Deole 43 Mr. Gaurav Mohol 44 Ms. Shubhangi Agbote 45 Ms. Swati Nimbalkar 46 Ms.Kalpana Kedar 47 Ms. Asmita Patil 48 Mr. Varun Kawathekar 49 Mr. Mayur Jadhav 50 Ms. Priya Amane 51 Mr. Amlekar Purushottam 52 Ms. Anuja Mahajan 53 Mr. Yogesh Nakate 54 Ms. Tejashri Aphale 55 Mr. Shailesh Mohite 56 Mr. Vishal Gholap 57 Mr. Rahul Mali 58 Mr. Kapli Salgar 59 Mr. Nikhil jadhav 60 Mr. Amar Deshmukh 61 Mr. Anup C. Balharpure RTM Nagpur University, Nagpur 62 Ms. Aditi S. Pande RTM Nagpur University, Nagpur 63 Mr. Shailesh Kumbhar 64 prof. V.P.Labade 65 Mr. Aditya Anand 66 prof. V.V.Velhal Dr. D.Y.Patil College of Engineering, Pimpari Dr. D.Y.Patil College of Engineering, Pimpari 67 Prof. S.K.Shinde YCI, Satara 68 Mr. Vipul D. Patankar Poona College, Pune-411001
Statistical analysis of Feedback given by participants Quality Points Superb 10 Scale of points Excellent Very good Good 9 8 7 Fair 6 Tolerable 5 Poor 4 Bad 3 Very bad 2 No Comment 1
News : Prof. S.R.Chaudhari Vice Principal Head, Department of Electronic Science Dr. R.S.Zunjarrao Principal
To Prof. Sachin Patkar Principal Investigator, e- prayog, Virtual Labs(Electronics) IIT, Bombay Subject: Request for Kryeton CPLD and Aurum PIC microcontroller boards. Dear Sir, Department of Electronic Science, P.E. Society s, Modern College of Arts Science and Commerce Pune-5 and e- prayog, Virtual Labs(Electronics) jointly organized two days state level workshop on digital system design using VHDL on CPLD boards on 10th and 11th February 2012. Workshop was successful due to cooperation rendered by team of e- prayog, Virtual Labs (Electronics). We are thankful to Virtual Lab for identifying us as a Nodal center. We are sending e-copy of the report to Virtual Lab. We received 11 CPLD boards in September 2010. We conducted three workshops (University of Pune, University of Nagpur and Modern College, Pune-5) using CPLD boards. We developed daughter boards, which were used in above workshops. In the workshop, Mr. Abhishek Kamath, IIT, introduced Kryeton CPLD board. We found that, board is very useful to conduct complex practicals. We request you to arrange five Kryeton CPLD boards. We assure you we will make best use of these boards similar to EPM3064 boards. In the workshop 14 Helium V1.1 CPLD boards and 10 Aurum PIC boards were distributed to participating institutes. We request to arrange Ten Aurum PIC boards to our College and four Aurum PIC boards for distributions to four institutes participated in State level workshop. We expect similar cooperation in future. With warm regards, Prof. S.R.Chaudhari Vice Principal and Head, Department of Electronic Science Dr. R.S.Zunjarrao Principal