CSE 241 Digital Systems

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CSE 241 Digital Systems Spring 2018 Course Description A course in digital principles which includes the following topics: fundamentals of digital logic, number systems, codes, computer arithmetic, Boolean algebra, minimization techniques, basic components of digital circuits such as logic gates and flip-flops, design of combinational and sequential circuits, memory devices, and programming logic. Recommended for sophomore-level students. Learning Outcomes Understand and apply Boolean Algebra Understand logic gates and their operation Understand Karnaugh maps and apply them to simplify logic expressions Understand signed and unsigned integer representation and arithmetic MSI circuit decoders, multiplexers and design of combinational circuits Flip-flops and sequential circuit synthesis Verilog hardware description language, synthesis and simulation Course Prerequisites None, however familiarity with using a computer is necessary. If you do not feel comfortable with word processors, web browsers, or general computing this course may not be appropriate at this time for you and you should speak with the instructor immediately. Textbook and Materials Recommended: Digital Design: With an Introduction to the Verilog HDL by M. Morris Mano and Michael D. Ciletti, Prentice Hall; 6 edition (March 2017), ISBN-13: 978-0134549897 Required: You will also buy a lab-kit of components customized for the course, there are two options. Do not by both. If you choose not to buy a kit, the list of components is below and you are expected to have them, and can purchase them from sources of your choice. Option 1: You can buy at Jameco using one collective part number: 2244818 It costs $21.79 + shipping and handling.

Option 2: The second part that we will use is an Arduino Uno. This is a very versatile and highly useful microcontroller board. This is often used in prototyping small circuits. You can buy both this option at Jameco using one collective part number: 2244800. If you purchase this kit you do not need to purchase the one above. It costs $43.95 + shipping and handling. Materials list: Schedule Lecture: 10 am - 10:50 am, MWF, NSC 201 Recitation: R1: R 8 pm - 8:50 pm R2: T 6 pm - 6:50 pm R3: W 3 pm - 3:50 pm R4: R 9 am - 9:50 am R5: F 3 pm - 3:50 pm R6: M 8 am - 8:50 am R7: W 7 pm - 7:50 pm

R8: M 2 pm - 2:50 pm R9: R 10 am - 10:50 am R10: F 12 pm - 12:50 pm R11: T 8 pm - 8:50 pm R12: M 6 pm - 6:50 pm R13: F 5 pm - 5:50 pm Attendance Lectures: Students are required to attend lectures. The absence will risk missing of important content and information. In lecture quizzes may not be announced ahead of time. If you do not show up for an exam or quiz without previous arrangements barring extreme unforeseeable circumstances, then you will not be allowed to make up the assignment. Recitations/Labs: If you complete your lab earlier than the full time assigned, attendance in the recitation is not required. When labs are assigned it is mandatory that you attend your assigned recitation section to perform your lab. Prelabs (if applicable) can only be signed off during your assigned lab section during the first of the recitations assigned for that specific lab. If you must miss your section, speak with your TA as soon as possible. Sections are full so attending other sections is not allowed without express permission. You are to use this time to work on your lab assignments however you may need to spend additional time outside of the recitation to complete the work. You may also use this time to work on other course related assignments. Instructor Contact Information Dr. Jennifer Winikus Email: jwinikus@buffalo.edu Website: www.cse.buffalo.edu/~jwinikus Office Phone: 716-645-4757 Office: Davis 351 Office Hours Unless instructed that they have changed. To Be Announced, Davis 351 By appointment, email to arrange. TAs will provide additional office hours which will be announced.

Academic Content This is a tentative list of topics: Number Systems Signed Arithmetic Boolean Arithmetic Karnaugh Maps Combinational Logic Logic Gates Sequential Logic Verilog Design Program Outcome Support: Program Outcome Support 0: Not Supported, 1: Minimally Supported, 2: Supported, 3: Strongly Supported CEN Program Outcome a b c d e f g h i j k Support Level 3 0 3 0 3 0 0 0 0 0 3 CS Program Outcome a b c d e f g h i j k Support Level 3 0 0 0 0 0 0 0 3 0 0 Grading Policies Your grade will be comprised of: 20 % Exam 1 30 % Exam 2 15 % Homework, Quizzes, and other assignments 35 % Laboratory Assignments Extra credit opportunities may be offered. Your final score for the course will be converted into a letter grade as follows: A: 100 94 A-: 93 90 B+: 89 87 B: 86 84 B-: 83 80

C+: 79 77 C: 76 74 C-: 73 70 D: 69 60 F: 59 0 The instructor reserves the right to curve grades if appropriate and as they choose. Incompletes (I/IU): The course follows the university undergraduate incomplete policy. A grade of incomplete ( I ) indicates that additional coursework is required to fulfill the requirements of a given course. Students may only be given an I grade if they have a passing average in coursework that has been completed and have well-defined parameters to complete the course requirements that could result in a grade better than the default grade. An I grade may not be assigned to a student who did not attend the course. Prior to the end of the semester, students must initiate the request for an I grade and receive the instructor s approval. Assignment of an I grade is at the discretion of the instructor. The instructor must specify a default letter grade at the time the I grade is submitted. A default grade is the letter grade the student will receive if no additional coursework is completed and/or a grade change form is not filed by the instructor. I grades must be completed within 12 months see the Incomplete Grade Policy for the schedule. Individual instructors may set shorter time limits for removing an incomplete than the 12-month time limit. Upon assigning an I grade, the instructor shall provide the student specification, in writing or by electronic mail, of the requirements to be fulfilled, and shall file a copy with the appropriate departmental office. Students must not re-register for courses for which they have received an I grade Collaboration Policies Unless explicitly told, all work is to be done independently with only the assistance of TAs and the instructor. You may discuss the general concepts of assignments and what the question asks for with other students but you must not discuss answers. Unauthorized collaboration will result in an F in the course as a violation of academic integrity. Exam Policy There will be 2 exams. Two exams will be in class, the final exam is scheduled by the registrar. You must have a valid ID with you at the time of the exam (UB Card will suffice) and your own writing tools. You can not borrow pens or pencils during the exam. During the exam there is to

be no talking or looking at your phone, doing so may result in an automatic F on the exam based on the incident. Any accommodations must be made in advanced barring extraordinary circumstances. Due Dates All submissions will be made on UBLearns. Late work: No late work will be accepted. You have a 24 hour grace period after the due date where you can submit still at no penalty, after that close out, work will not be accepted. No work will be accepted after midnight on Friday of the last week of classes barring extraordinary circumstances. This includes regrade requests. If a review of your assignment grading is desired, you have 1 week from the time the grade is released to requesting a regrade. Corrections are not allowed, with the exception of the special policies for Exam 1 (these will be detailed prior to the exam). Email Policy Students are responsible for email sent to their official University at Buffalo email address. Communication will not be done with non-university email addresses. A level of professionalism is expected with all communications. Accessibility Resources If you have any disability which requires reasonable accommodations to enable you to participate in this course, please contact the Office of Accessibility Resources, 60 Capen Hall, 716-645-2608, and also the instructor of this course. The office will provide you with information and review appropriate arrangements for reasonable accommodations. University Policies You are expected to adhere to all university policies, including those listed below and not listed.

Academic Integrity Policy: http://undergrad-catalog.buffalo.edu/policies/course/integrity.html University Policy on Accommodations: https://policy.business.buffalo.edu/policy%20library/reasonable%20accommodation.pdf The Office of Equity, Diversity and Inclusion provides many resources including the following policies to be followed: Discrimination and Harassment: http://www.buffalo.edu/administrative-services/policy1/ub-policy-lib/discrimination-harassm ent.html Reasonable Accommodation: http://www.buffalo.edu/administrative-services/policy1/ub-policy-lib/reasonable-accommodat ion.html Religious Accommodation and Expression: http://www.buffalo.edu/administrative-services/policy1/ub-policy-lib/religious-accommodatio n-expression.html Departmental Academic Integrity Policy https://engineering.buffalo.edu/computer-science-engineering/undergraduate/resources-for-c urrent-students/academic-integrity-students.html Student Code of Conduct http://www.buffalo.edu/content/dam/www/studentlife/units/uls/judicial-affairs/ub-student-c ode-of-conduct.pdf Classroom Behavior Expectations https://catalog.buffalo.edu/policies/obstruction.html

Departmental Statement on Academic Integrity in Coding Assignments and Projects All academic work must be your own. Plagiarism, defined as copying or receiving materials from a source or sources and submitting this material as one's own without acknowledging the particular debts to the source (quotations, paraphrases, basic ideas), or otherwise representing the work of another as one's own, is never allowed. Collaboration, usually evidenced by unjustifiable similarity, is never permitted in individual assignments. Any submitted academic work may be subject to screening by software programs designed to detect evidence of plagiarism or collaboration. It is your responsibility to maintain the security of your computer accounts and your written work. Do not share passwords with anyone, nor write your password down where it may be seen by others. Do not change permissions to allow others to read your course directories and files. Do not walk away from a workstation without logging out. These are your responsibilities. In groups that collaborate inappropriately, it may be impossible to determine who has offered work to others in the group, who has received work, and who may have inadvertently made their work available to the others by failure to maintain adequate personal security. In such cases, all will be held equally liable. Departmental Policy on Violations of Academic Integrity The CSE Department has a zero-tolerance policy for AI violation. All AI violation cases will be reported to the department, school and university, and recorded. Even the 1st offense will receive "F" for the course, unless the instructor deems it appropriate to reduce the penalty. Subsequent violation of AI in any form and in any other course will automatically result in a "F" grade, with no exception.

Tentative Schedule The schedule and content is subject to change. Please pay attention to announcements for details about important dates. Week Date Material 1 M- Jan 29 Introduction 1 W- Jan 31 Introduction to Number Systems 1 F- Feb 2 Signed Arithmetic 2 M- Feb 5 2 W- Feb 7 Boolean Arithmetic 2 F- Feb 9 Floating Point Basics 3 M- Feb 12 Simplification of Boolean Equations and Logic Gates 3 W- Feb 14 3 F- Feb 16 4 M- Feb 19 K-Maps and Combinational Logic 4 W- Feb 21 4 F- Feb 23 5 M- Feb 26 5 W- Feb 28 5 F- March 2 6 M- March 5 Tentative Exam 1 Review Date 6 W- March 7 Tentative Exam 1 Date 6 F- March 9 Decoders, and Muxes 7 M- March 12 7 W- March 14

7 F- March 16 8 M- March 19 No Class - Spring Break 8 W- March 21 No Class - Spring Break 8 F- March 23 No Class - Spring Break 9 M- March 26 Sequential Logic 9 W- March 28 9 F- March 30 10 M- April 2 10 W- April 4 More Sequential Logic 10 F- April 6 11 M- April 9 11 W- April 11 11 F- April 13 12 M- April 16 12 W- April 18 12 F- April 20 13 M- April 23 13 W- April 25 13 F- April 27 14 M- April 30 Verilog 14 W- May 2 14 F- May 4 More Verilog 15 M- May 7 15 W- May 9 15 F- May 11 Last day of classes- Final exam review

M- May 14 Final Exam Week- No Class W- May 16 Final Exam Week- F- May 18 Final Exam Week- No Class Final exam is scheduled (this is subject to change and is controlled by the registrar)- May 18, 8-11am, NSC 201 Important Dates First Day of Classes: Monday January 29 Last Day to Drop/Add: Monday February 5 Last Day to Resign: Friday April 20 Last Day of Classes: Friday May 11