f14s_elct7.fm - 1 Week Starting Date Subject Objectives Electronics I SYLLABUS 1. August 25 Chapter 1 Introduction to Electronics Chapter 2 Solid State Electronics Materials 2. September 1 Chapter 3 Solid State Diodes 3. September 8 Chapter 3 Solid State Diode Circuits 4. September 15 Section 3.13 through 3.16 Rectifier circuits. 5. September 22 Chapter 4 Field Effect Transistors Midterm#1 6. September 29 Chapter 6 Introduction to Digital Electronics. 7. October 6 Chapter 7 Static CMOS: 7.1 and 7.2 CMOS Inverter circuit. 8. October 13 7.2 CMOS Inverter circuit. Section 12.3 DAC and 12.4 ADC 9. October 20 Chapter 7 CMOS: 7.5 CMOS NAND and NOR Gates. 10. October 27 Chapter 7 CMOS: 7.6 through 7.10 Design of Complex gates 11. November 3 Chapter 5 Bipolar Junction Transistor. Midterm#2 12. November 10 BJT & BJT Inverter 13. November 17 BJT Inverter. Chapter 9 BJT Logic Gate Circuits. 14. November 24 Chapter 9 BJT Logic Gate Circuits. 15. December 1 Chapter 8 Solid State Memory Circuits. 16. December 8 Chapter 8 CMOS Storage Circuits. Course review. Prerequisites Understanding of the operation of electronic circuit components and their piecewise linear models. Knowledge of basic logic and analog circuits, and digital circuit families. Hands-on experience in mathematical analysis, simulation, test, and measurement of electronic circuits using modern tools to collect data for, and eventually prepare professional level reports. EECS 2300 Electric Circuits (with a grade of C or higher, if you want your instructor s advice). Textbook: Jaeger/Blalock: Microelectronic Circuit Design - 4th ed., McGraw-Hill, 2010, ISBN 0073380458 / 9780073380452. Suggested reading: Tuinenga, : SPICE a Guide to Circuit Simulation & Analysis Using PSpice, Prentice Hall, 1995. Exam policy: Two Midterm Exams (of which the first missed midterm is optional), and a mandatory comprehensive Final examination in the final s week. Points for the first missed midterm are transferred to the Final s point pool. Missed Final can be taken at the Final s place and time of any semester in which the course is offered. Missing all three examinations results in failing the course. Grading Policy: Homeworks /Lab/ two Midterms / Final = 10/24/30/36. Instructor: Homework grader: Dr. A. Johnson; office NI-2049; phone x8176, anthony.johnson@utoledo.edu. Mr. Neel Kamal Bandreddy, email : neelkamal.bandreddy@rockets.utoledo.edu, office hours T 6:00 to 7:00PM and R 3:00 to 4:00PM, office. Location of graders office hours: Nitschki Hall, second floor bridge between the southern an middle towers?
f14s_elct7.fm - 2 2. Lab information 2.1 Lab Room: NE-1018 - Electronics Lab 2.2 Schedule of Lab Hours: NE-1018 - Electronics Lab Section Time GA Office Office hours 3400:002 T 3:30-5:50 Nuwan Kumarasiri NE-1035 3400:003 R 3:30-5:50 Nuwan Kumarasiri NE-1035 3400:004 T 6:00-8:20 Abhishek Sahu abhishek.sahu@rockets.utoledo.edu 3400:005 R 6:00-8:20 Nuwan Kumarasiri NE-2042 MF 3-4:00PM MF 4-5.00.PM WF 3-4.00.PM 2.3 Schedule of Lab Assignments Lab Semester Assignment week 2.4 Description of Lab Experiments Description of Lab Experiments: #1 through #8 is provided in the Electronics Lab Manual I, by Dr. R.King, available from the campus bookstore. Descriptions of Lab Assignments #9, #10, #11 and #12 are posted on the course webpage. Prelab Assignment. To improve the ratio of the time spent building the experimental circuit on the protoboard to the time devoted to the educational experience through experiments on the built circuit, students are required to prepare (carries 25% of the grade) a good quality, computer generated drawing of the physical layout of circuits to be built. Lab report: Computer generated Lab reports are required for full credit. Grading Policy: Prelab Assignment / Lab Experiment / Lab Report = 0.5 / 0.75 / 0.75. Experiment No.1 3 #1 Using the Digital Storage Oscilloscope No.2 4 #3 Diodes No.3 5 #11 DC Analysis of a Diode Circuit Using SPICE No.4 6 #13 Simulation of a bridge rectifier using SPICE No.5 7 #14 Diode Reverse Recovery as Observed using SPICE No.6 8 #6 SPICE modelling of MOSFET and JFET No.7 8&14 #7 Characterizing Digital Logic gates: VTC, NM and t PD No.8 10 #9 Analog/Digital Conversion No.9 11 Simulation of a CMOS two-input NAND gate using SPICE No.10 12 Pass Transistor Logic Gates No.11 13 Desig of an Experiment No.12 15 Simulation of a TTL two-input NAND gate using SPICE
f14s_elct7.fm - 3 3. Homework schedule 3.1 Overview of the Required Minimal Homework Problem set The numbers in the Problem Set Contents column of the following table refer to the problem designations in the course Textbook; descriptions of unnumbered assignments/problems will be made abvailable on the course webpage. Semester Set # Problem Set Contents week due #1 Analysis of problem areas in the exams of the last two semesters posted at the course website: www.eecs.utoledo.edu/~ajohnson. #2 2.2, 2.3, 2.7, 2.9, 2.12, 2.23, 2.27 2 #3 2.45, 2.52, 3.1, 3.2, 3.8, 3.13, 3.18; 2.50 - bonus point, 3 #4 3.22, 3.26, 3.35, 3.43, 3.48, 3.51, 3.56, 4 #5 3.58, 3.66, 3.69, 3.71, 3.72, 3.73, 3.77. 5 #6 3.78, 3.83, 3.86, 3.92, 3.100(a), 3.109. 6 #7 4.2, 4.4, 4.6, 4.8, 4.10, 4.15, 4.22. 8 #8 Analysis of the characteristic points on the CMOS inverter VTC. 9 #9 6.1, 6.2, 6.3, 6.7, 6.8, 6.9, 6.11. 11 #10 Calculation of I/O Parasitic Capacitances of the CMOS inverter circuit. 12 #11 5.1, 5.2, 5.4, 5.13, 5.31, 5.32, 5.35. 13 #12 Analysis of the characteristic points on the BJT inverter VTC. 15 1 This required minimal homework set is the result of a compromise made with the past generations of students who had complained that the double number of problems presented them with too much work. Current students willing to acquire a solid knowledge of the subject are strongly advised to work on solving twice as many problems, including those from past exams posted on the course homepage. 3.2 Policy on homework assignment credit For full credit on problem solutions: 3.21 give answers to all questions, 3.22 show the original and auxiliary circuit models with circuiit elements labelled by their parameters (which are not the parameter values), 3.23 indicate in the circuit model the positive reference directions of all voltages and currents which are involved in the solution process, 3.24 provide all symbolic and numerical expressions whose evaluation produces shown numerical results, 3.25 apply the determinant method for solving sets of simultaneous algebraic equations.
f14s_elct7.fm - 4 3.3 Policy on submission of Homework Reports 3.31 This policy promotes good planning habits. The fact that something went wrong the morning of the due day does not make a case for delaying the due time. We ought to be prepared for the day when something unusual happens. 3.32 All homework reports (solutions) are due at the beginning of the last class of the week. 3.33 In order to discourage the practice of preparing the reports during the time scheduled for classes, the absolute deadline for handing in the homework reports is five minutes after the time scheduled for the beginning of the class. 3.34 Homework reports handed in after the deadline, but before the beginning of the first class of the next week are accepted for half credit. All homework reports not handed in at the regular time are to be handed to the homework grader. 3.35 Homework reports are not considered turned in if they are not completly covered by a completely filled out cover sheet posted at the course webpage. 4. ABET Documentation 4.1 EAC Student Learning Objectives 1 Students will be able to apply the large signal method of analysis to electronic circuits that contain nonlinear circuit elements: diodes, FETs and BJTs. 2. Students will be able to apply the SPICE simulation method of analysis to electronic circuits that contain nonlinear circuit elements: diodes, FETs and BJTs. 3. Students will be able to design FET and BJT inverter circuits with a required noise margin and fan-out, inverters of minimum size, with equal rise and fall times, and with specified logic threshold voltage value. 4. Students will be able to explain the tradeoffs for lowering power dissipation in digital electronic circuits. 5. Students will be able to analyse combinational logic circuits to determine the Boolean function implemented by the circuit, 6. Students will be able to design combinational static CMOS gates so that they implement a desired Boolean function, and to design the transistor aspect ratios so that the CMOS gate has the same rise and fall times as the reference inverter. 7. Students will be able to give examples of the three established principles of encoding the logic/ numeric values in memory cells: by the state of a bistable circuit, by an electrical charge on a capacitance, and by a FET s threshold voltage value. 8. Students will be able to state the challenges and the complexity tradeoffs in the design of modern memory arrays. 9. Students will be able to state the design principles used in legacy TTL and ECL integrated circuits. 10. Students will be able to conduct experiments in order to collect, analyze, and interpret data.
f14s_elct7.fm - 5 11. Students will be able to explain the properties of semiconductor materials and the mechanisms of charge transportation in semiconductor materials. 12. Students will be able to design an experiment to measure the propagation delay of a representative of two families of widely used digital logic gates (4xxx series CMOS and 74LSxx series TTL). 13. The student will be able to function effectively on a team with effectiveness being determined as documented in lab reports, instructor observations, and peer ratings. 4.2 ABET Outcomes Supported EAC CAC Outcome Supporting SLOs Outcome Supporting SLOs a 11 b 10, 12 c 3, 6 d 13 e 5 i 9 j 4, 7, 8 k 1, 2 None of CAC outcomes supported 4.3 ABET Description of EAC Outcomes a - b - c - d - e - i - j - k - An ability to apply knowledge of mathematics, science, and engineering. An ability to design and conduct experiments, as well as to analyze and interpret data. An ability to design a system, component, or process to meet desired needs within realistic constraints such as economic, environmental, social, political, ethical, health and safety, manufacturability, and sustainability. An ability to function on multidisciplinary teams. An ability to identify, formulate, and solve engineering problems. A recognition of the need for, and an ability to engage in life-long learning. A knowledge of contemporary issues. An ability to use the techniques, skills, and modern engineering tools necessary for engineering practice.