Modern Placement Techniques

Transcription

1 Modern Placement Techniques

2 MODERN PLACEMENT TECHNIQUES MAJID SARRAFZADEH Computer Science Department University of California, Los Angeles MAOGANG WANG Cadence Design Systems, Inc. XIAOJIAN YANG Computer Science Department University of California, Los Angeles Springer-Science+Business Media, B. V.

3 ... " Electronic Services < Library of Congress Cataloging-in-Publication Data Sarrafzadeh, Majid Modern placement techniques/majid Sarrafzadeh, Maogang Wang, Xiaojian Yang p.cm. Includes index. l.integrated circuit layout. I. Wang, Maogang. 11. Yang, Xiaojian. Ill. Title TK S '5--dc21 ISBN ISBN (ebook) DOI / Copyright 2003 by Springer Science+Business Media Dordrecht Originally published by Kluwer Academic Publishers in Softcover reprint of the hardcover 1st edition 2003 All rights reserved. No part of this work may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, microfilming, recording, or otherwise, without the written permission from the Publisher, with the exception of any material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work. Printed on acid-free paper.

4 Contents Preface Acknowledgments l. INTRODUCTION 1 1 Background 3 2 Physical Design Flow 7 3 Placement Methodology 11 4 Placement Cube 13 5 Organization of the Book REVIEW OF PLACEMENT WORK 17 1 Partitioning 17 2 Placement: Constructive or Iterative 27 3 Placement Algorithms 28 4 Detailed Placement 37 5 Congestion-Driven Placement 38 6 Timing-Driven Placement DRAGON: A PLACEMENT FRAMEWORK 57 1 Placement Using Net-cut and Wirelength Objective 58 2 Dragon: A Standard-cell Placement Tool 72 3 Detailed Implementation of Dragon 79 4 Summary CONGESTION ESTIMATION 91 1 Introduction 91 2 Rent's Rule 92 vii xi

5 vi 3 Peak Congestion Analysis 93 4 Regional Congestion Estimation 97 5 Summary CONGESTION MINIMIZATION Introduction Congestion in Placement Congestion Reduction in Detailed Placement Approximation Algorithm for ILP Congestion Reduction in Detailed Placement Summary WHITE SPACE ALLOCATION Introduction Allocation Approach White Space Allocation in Placement Placement Snapshots Summary TIMING-DRIVEN PLACEMENT Introduction Preliminaries Slack Assignment Multi-Level Placement with Predefined Hierarchy Summary SOFTWARE, BENCHMARKS AND RESULTS Dragon Placement Tool Benchmarks Dragon's Results MACRO-CELL PLACEMENT Introduction Possibilities and Pitfalls Overview of Previous Work Summary CONCLUSION 175

6 Preface MAJID SARRAFZADEH As the technology evolves to the range of deep sub-micron (DSM), interconnects become mbre and more important. Conventional physical design is becoming a limiting factor in the whole VLSI design flow. In high-end systems such as supercomputers, mainframes, medical and military electronics, more than 50% of the total system delay is usually due to interconnection, and the share of interconnection delay keeps increasing as the feature size decreases. Due to rapid development in the VLSI technology, the average transistor count in a chip is increased enormously. The well known Moore's Law, which predicts that the number of transistors on a chip would grow exponentially over relatively brief periods of time, is very accurate. Over the past thirty years, the number of transistors per chip has doubled every months. On the other hand, most physical design problems are NP-hard. This fact implies that a polynomial time algorithm which can optimally solve these problems is highly unlikely. Almost all existing physical design tools are based on heuristics. These heuristics might be very successful at the time when they were released/published. However, with the daily increasing complexity of VLSI design and the new DSM technology, most conventional heuristics cannot handle the problem as effectively as they used to. Electronics industry requires new physical design algorithms that can deal with today's large industrial VLSI design and allow designers to design high performance integrated circuits. Electronic physical design is an art based on the science of establishing interconnections and fulfilling system functions by placing modules and interconnection within a chip or package. Placement is the back-bone of the whole physical design flow. This book focuses on the placement

7 viii problem in VLSI physical design methodology and automation. It explores various placement problems and approaches of minimizing interconnect length, congestion and timing. We will also review fundamental placement techniques with emphasis on a state-of-the-art placement tool called Dragon. Placement problem has been studied for more than thirty years. Major advances have been made on this topic. Yet there are some fundamental questions unanswered. In this book the placement problem is viewed as a four dimensional cube representing four important elements of placement problem: cost function, algorithm, netlist granularity and layout coarseness. An effective methodology understands the interaction between these placement elements and picks the right combination of them. The cost function is the measurement of placement goals. Typical cost functions include cut, wirelength (manhattan, linear, quadratic), congestion, timing and crosstalk. Simply minimizing one cost function, e.g., wirelength, does not account for the goals in placement. Modern placement problem are more complex and involves several cost functions at the same time. Many algorithms have been proposed for placement problem. Successful placement algorithms include bipartitioning algorithm, quadratic algorithm, simulated annealing and force-direct algorithm. We will discuss these algorithms in Chapter 2. Each algorithm has its advantages and disadvantages. The selection of the algorithms for placement problem depends on the goals and the constraints of the problem, and should be changed for different situations. Netlist granularity indicates the level of abstraction for the circuit interconnects. For large scale designs, it is computational expensive to directly apply any algorithm on the original netlist. Some forms of net list abstraction, e.g., partitioning or clustering, is indispensable to efficiently solve the problem. Layout coarseness represents the intermediate status of the placement process. It is related to top-down placement flow, which is the most popular framework for solving today's large scale placement problem. In top-down placement flow, the circuits are divided into sub circuits and the sub circuits are placed into the placement regions of the entire area. The sizes of the subcircuits decrease as the placement flow goes deeper. Layout coarseness indicates the level of the top-down flow, or the position of the current placement in the whole process. It is usually represented using the placement grid, e. g., 2 x 2,4 x 4, 16 x 20. Note that layout coarseness is not the same concept as netlist granularity. The number of placement regions and the number of nodes in the abstracted

8 PREFACE ix netlist are not necessarily the same. At one intermediate placement stage, we may have a coarse placement with highly granulated netlist. In placement process, there is no single cost function or algorithm that guarantees success. Hence it is crucial to choose the right algorithm to optimize the right cost function at the right time. This needs a fully understanding of different aspects for the placement problem. Today's placement tools use this mechanism, but in an ad-hoc way. Fundamental research is required to devise the methodology which systematically suggests the solution to the placement problem. Organization of the Book The overall goal of this book is to provide expertise in the area of VLSIjCAD placement. The book introduces the placement problem and gives an overview of existing placement algorithms, techniques, and methodologies, with the emphasis on recent advances for placement problem, including congestion-driven, timing-driven, mixed macro-cell and standard-cell placement. Then we present a successful placement tool, Dragon, with detailed algorithm descriptions for wirelength, congestion and timing optimization. We also show related placement benchmarks and results produced by Dragon and other placement tools. The first chapter (introduction) gives a brief introduction of the physical design process and placement problem. A placement methodology based on placement cube is presented and explained. The next chapter (Chapter 2) is a detailed survey on previous placement algorithms. All categories of existing algorithms, along with their variations, are discussed. Techniques for wirelength-driven placement, congestion-driven placement, timing-driven placement and detailed placement algorithms are reviewed in this chapter. We focus on recent effective placement methods as well as classical approaches. Chapter 3 presents an effective placement framework and a provably good placement tool: Dragon. Basic structures of Dragon and implementation details are described. Chapter 4 and Chapter 5 present new techniques on congestion estimation and congestion minimization, respectively. Chapter 6 shows a white space allocation method for improving layout routability. Chapter 7 presents a novel timing driven placement method. Chapter 8 presents benchmark suites used for wirelength, congestion and timing optimization. The results by Dragon and other placement tools on these benchmarks are reported. Chapter 9 talks about an important topic in modern placement problem: mixed macrocell and standard-cell placement. It contains an overview of existing effective algorithms for mixed mode placement. At the end, Chapter 10 gives the conclusion of this book.

9 To Our Families.. - Majid - Maogang - Xiaojian

10 Acknowledgments Dragon is the result of more than ten years of research in the area of placement. Many students of Majid Sarrafzadeh (at Northwestern and at UCLA) have had direct and indirect contributions to the materials presented to this book including Gustavo Tellez, David Knol, Ryan Katner, Elaheh Bozorgzadeh, Kenneth Eguro and Bo-Kyung Choi.